| Message ID | 20180509085928.2023-7-m.szyprowski@samsung.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v7,1/7] drm/exynos: ipp: Add IPP v2 framework | expand |
2018년 05월 09일 17:59에 Marek Szyprowski 이(가) 쓴 글: > From: Andrzej Pietrasiewicz <andrzej.p@samsung.com> > > There are 3 scaler devices in Exynos5420 SoCs, all are a part of MSCL > power domain. MSCL power domain and SYSMMU controllers (two per each > scaler device) have been already added to exynos5420.dtsi earlier, > so bind them to newly added devices. > > Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Inki Dae <inki.dae@samsung.com> Thanks, Inki Dae > --- > arch/arm/boot/dts/exynos5420.dtsi | 36 +++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi > index 717c0e6474f5..f4e8c5823bc2 100644 > --- a/arch/arm/boot/dts/exynos5420.dtsi > +++ b/arch/arm/boot/dts/exynos5420.dtsi > @@ -673,6 +673,36 @@ > iommus = <&sysmmu_gscl1>; > }; > > + scaler_0: scaler@12800000 { > + compatible = "samsung,exynos5420-scaler"; > + reg = <0x12800000 0x1294>; > + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clock CLK_MSCL0>; > + clock-names = "mscl"; > + power-domains = <&msc_pd>; > + iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>; > + }; > + > + scaler_1: scaler@12810000 { > + compatible = "samsung,exynos5420-scaler"; > + reg = <0x12810000 0x1294>; > + interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clock CLK_MSCL1>; > + clock-names = "mscl"; > + power-domains = <&msc_pd>; > + iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>; > + }; > + > + scaler_2: scaler@12820000 { > + compatible = "samsung,exynos5420-scaler"; > + reg = <0x12820000 0x1294>; > + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clock CLK_MSCL2>; > + clock-names = "mscl"; > + power-domains = <&msc_pd>; > + iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>; > + }; > + > jpeg_0: jpeg@11f50000 { > compatible = "samsung,exynos5420-jpeg"; > reg = <0x11F50000 0x1000>; > @@ -807,6 +837,7 @@ > interrupts = <22 4>; > clock-names = "sysmmu", "master"; > clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; > + power-domains = <&msc_pd>; > #iommu-cells = <0>; > }; > > @@ -816,6 +847,7 @@ > interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "sysmmu", "master"; > clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; > + power-domains = <&msc_pd>; > #iommu-cells = <0>; > }; > > @@ -825,6 +857,7 @@ > interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "sysmmu", "master"; > clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; > + power-domains = <&msc_pd>; > #iommu-cells = <0>; > }; > > @@ -835,6 +868,7 @@ > interrupts = <27 2>; > clock-names = "sysmmu", "master"; > clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; > + power-domains = <&msc_pd>; > #iommu-cells = <0>; > }; > > @@ -845,6 +879,7 @@ > interrupts = <22 6>; > clock-names = "sysmmu", "master"; > clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; > + power-domains = <&msc_pd>; > #iommu-cells = <0>; > }; > > @@ -855,6 +890,7 @@ > interrupts = <19 6>; > clock-names = "sysmmu", "master"; > clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; > + power-domains = <&msc_pd>; > #iommu-cells = <0>; > }; > > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, May 09, 2018 at 10:59:27AM +0200, Marek Szyprowski wrote: > From: Andrzej Pietrasiewicz <andrzej.p@samsung.com> > > There are 3 scaler devices in Exynos5420 SoCs, all are a part of MSCL > power domain. MSCL power domain and SYSMMU controllers (two per each > scaler device) have been already added to exynos5420.dtsi earlier, > so bind them to newly added devices. > > Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > --- > arch/arm/boot/dts/exynos5420.dtsi | 36 +++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > Thanks, applied. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 717c0e6474f5..f4e8c5823bc2 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -673,6 +673,36 @@ iommus = <&sysmmu_gscl1>; }; + scaler_0: scaler@12800000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12800000 0x1294>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL0>; + clock-names = "mscl"; + power-domains = <&msc_pd>; + iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>; + }; + + scaler_1: scaler@12810000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12810000 0x1294>; + interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL1>; + clock-names = "mscl"; + power-domains = <&msc_pd>; + iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>; + }; + + scaler_2: scaler@12820000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12820000 0x1294>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL2>; + clock-names = "mscl"; + power-domains = <&msc_pd>; + iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>; + }; + jpeg_0: jpeg@11f50000 { compatible = "samsung,exynos5420-jpeg"; reg = <0x11F50000 0x1000>; @@ -807,6 +837,7 @@ interrupts = <22 4>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; @@ -816,6 +847,7 @@ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; @@ -825,6 +857,7 @@ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; @@ -835,6 +868,7 @@ interrupts = <27 2>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; @@ -845,6 +879,7 @@ interrupts = <22 6>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; @@ -855,6 +890,7 @@ interrupts = <19 6>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + power-domains = <&msc_pd>; #iommu-cells = <0>; };