From patchwork Wed Feb 21 10:15:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 129010 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp451241ljc; Wed, 21 Feb 2018 02:15:44 -0800 (PST) X-Google-Smtp-Source: AH8x224QTSniPx801eVWiehyQ/P3SDjMQuPZ0ag96ziLJEAzUUanuqrKTpUyLDQCEJtkcSfl8V+v X-Received: by 2002:a17:902:9693:: with SMTP id n19-v6mr2656205plp.69.1519208144483; Wed, 21 Feb 2018 02:15:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519208144; cv=none; d=google.com; s=arc-20160816; b=0lsn4Qo58tjrOW9GN556tMEZj2lV2UQIbO68El1hKn/7CT98zDW+OJ+o0N1TkY/lGz VoLkaMwJ/BMeUJeSC8nD+ozcMwPAdyzjm2JD73opPzjPJvnX/muv6rk2/xAuuRuW3Uhv 4TWMaGecYmo6Hk83De8RvV1uc5rvlH9tth9CoSvlpVqCNMZZXUk8VkBERKDEteI7Mv8x 5SPykKD4caoLIz37w4eTiiu8l8igBVYfgk3eR4ba/D6se5jmGu9GKSg5HEQ1Ce608vl/ vEhqsr0bOkLVSZ19HeIBNpxuyIBVwysPAYNRgSl0Vyl+1qa1R8zZpFEh+RreV1KdciuF mUAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:cms-type:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=4imyDg06i2lk+0fRVI3vnYrQCVEtdTWzHkB4icBVdOk=; b=G7FM5MW6Nh4NqFCQu58Pta87/LfqbHs6zIlsDrOCmonX9de51FoIeUYsSgN/au47KK 2PaXjI7O5OnfEboVWTpU/YgVNgo5mEZ2sd3Uy39Bmxdsde3pgN6driWhwElEs8/t/rhb IrLwp/z7uiu34Hjk7x5Nc85plrr1paKvOkbqJUeQbgMev/f3+xOe0YneHKOynhXw5y1Y iDJFbb/NpIq6jPFvFbW5tHCNQFYPpN4n3T6CrSXvHpszqR8GbHZ0KE/5HryFcpy2/OXk HLeu7xhCvgkBtIgt7SDSnrF0avDcVsjZISPK4mMQwvFvI5yoQvVaxIynvwliAp72c1aC XDEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@samsung.com header.s=mail20170921 header.b=fjYGf9iD; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=samsung.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d15si1180013pgv.822.2018.02.21.02.15.44; Wed, 21 Feb 2018 02:15:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@samsung.com header.s=mail20170921 header.b=fjYGf9iD; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=samsung.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932720AbeBUKPn (ORCPT + 3 others); Wed, 21 Feb 2018 05:15:43 -0500 Received: from mailout2.w1.samsung.com ([210.118.77.12]:53934 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932732AbeBUKPi (ORCPT ); Wed, 21 Feb 2018 05:15:38 -0500 Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20180221101536euoutp029f1bb4dbff64ce07bc6a5d1e04bdc02c~VT8A35zVn0096400964euoutp02i; Wed, 21 Feb 2018 10:15:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20180221101536euoutp029f1bb4dbff64ce07bc6a5d1e04bdc02c~VT8A35zVn0096400964euoutp02i DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1519208136; bh=XvauvFpRvYBFHn0xAQKNkldfCSKqkUJqZ5kecEyHWas=; h=From:To:Cc:Subject:Date:In-reply-to:References:From; b=fjYGf9iDj1vclKSDkrerapCDVIP3qqTnegltKmwL7sxXnN17/H/zsf+/IGitwE6VZ +aD3alD0Ge0bHVz1Btx6rwGzsKFiuYVUPmIHJ+nsnINjo5nnISCVK95BxGe7wnxRai o3KdK2sbGCgoXbcp+XdgdQeyRTAzThq31d0FbP/c= Received: from eusmges2new.samsung.com (unknown [203.254.199.244]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20180221101535eucas1p1a852d0ce170b272d938eb287966ad5ed~VT7-66foB0273302733eucas1p1i; Wed, 21 Feb 2018 10:15:35 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges2new.samsung.com (EUCPMTA) with SMTP id 0F.81.17380.6C64D8A5; Wed, 21 Feb 2018 10:15:34 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20180221101533eucas1p2c0fdc0b744b1e026906bd047507f5701~VT7_sJGF71444614446eucas1p2o; Wed, 21 Feb 2018 10:15:33 +0000 (GMT) X-AuditID: cbfec7f4-b4fc79c0000043e4-19-5a8d46c6470c Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id F0.04.04183.5C64D8A5; Wed, 21 Feb 2018 10:15:33 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P4H005K9WHT4SB0@eusync3.samsung.com>; Wed, 21 Feb 2018 10:15:33 +0000 (GMT) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 3/6] clk: samsung: exynos542x: Move PD-dependent clocks to Exynos5x sub-CMU driver Date: Wed, 21 Feb 2018 11:15:24 +0100 Message-id: <20180221101527.25554-4-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.15.0 In-reply-to: <20180221101527.25554-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrEIsWRmVeSWpSXmKPExsWy7djP87rH3HqjDKZN0rLYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6Mq/93MBd8i6h41nyeqYHxi3cXIyeHhICJxKn5a1i6GLk4hARWMEos2NbG DOF8ZpRYv/kOG0zV/Ktt7BCJZYwSy9f1MEE4DUwSP7obmUGq2AQMJbredoF1iAg4SHz+9JoR pIhZoI1J4uyB/UwgCWGBFIkdfXPBbBYBVYlPKyczgti8ArYS5yddYYFYJy+x+PtOoEEcHJwC dhI7X3KAzJEQ+MsqMW3fUUaIGheJM78/QNULS7w6voUdwpaRuDy5mwWioZ9R4t//l0wQzgyg hz62QlVZSxw+fpEVxGYW4JOYtG06M8g2CQFeiY42IYgSD4njH1czQ9iOEsfmzIP6fyKjxIpJ S5gmMEotYGRYxSieWlqcm55abJSXWq5XnJhbXJqXrpecn7uJERiTp/8d/7KDcdefpEOMAhyM Sjy8Lwx6ooRYE8uKK3MPMUpwMCuJ8FYK9UYJ8aYkVlalFuXHF5XmpBYfYpTmYFES543TqIsS EkhPLEnNTk0tSC2CyTJxcEo1MBYeuFLzo0RHcK/33/Bwt8LdG9I/HfVweC9y2UpzyqeNkjdi X7pvub5tRqaUk2FiQVjvj+sMRz1jL9fumc6Yfy1mPdNsq6PdYk6P1hcKLV+38cGDkvhnqVdd OW4/vHKrr+v28U/yCcfOTJ/EcMVA9c3SY8dlPZzOc2iLGIlYRYR4vzeuZ9B4cEqJpTgj0VCL uag4EQBKH447xQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpkluLIzCtJLcpLzFFi42I5/e/4Vd2jbr1RBqe3m1lsnLGe1eL6l+es FpPuT2CxOH9+A7vFx557rBYzzu9jslh75C67xeE37awOHB6bVnWyefRtWcXo8XmTXABzFJdN SmpOZllqkb5dAlfG1f87mAu+RVQ8az7P1MD4xbuLkZNDQsBEYv7VNnYQW0hgCaPEw8OWXYxc QHYTk0Rb93I2kASbgKFE19suMFtEwEHi86fXjCBFzAIdTBJ79j4ESwgLpEjs6JvLBGKzCKhK fFo5mRHE5hWwlTg/6QoLxDZ5icXfdwLVc3BwCthJ7HzJAbHYVmLa2rfsExh5FjAyrGIUSS0t zk3PLTbSK07MLS7NS9dLzs/dxAgMmG3Hfm7Zwdj1LvgQowAHoxIPr4VOT5QQa2JZcWXuIUYJ DmYlEd5Kod4oId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rznDSqjhATSE0tSs1NTC1KLYLJMHJxS DYwLs83KheQ29Lb+eLB9wVQWeReHn8Ylm1be8GT3kfY++ShHtJZtdsLXNvf1alM3tix2mGR2 XOroa/3dier3rVtcOE/UWcx/m8w242mz9a2kmmbVo1xquSVdbDo7uTiKRXY8Y7+l3vlpN+ve 7r2mc478SelfYP3hZa1lZm/hmw6VfYsUmWaqhiixFGckGmoxFxUnAgAXmWwZFAIAAA== X-CMS-MailID: 20180221101533eucas1p2c0fdc0b744b1e026906bd047507f5701 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180221101533eucas1p2c0fdc0b744b1e026906bd047507f5701 X-RootMTR: 20180221101533eucas1p2c0fdc0b744b1e026906bd047507f5701 References: <20180221101527.25554-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Clocks related to DISP, GSC and MFC blocks require special handling for power domain turn on/off sequences. Till now this was handled by Exynos power domain driver, but that approach was limited only to some special cases. This patch moves handling of those operations to clock controller driver. This gives more flexibility and allows fine tune values of some clock-specific registers. This patch moves handling of those mentioned clocks to Exynos5x sub-CMU driver instantiated from Exynos5420 driver. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5420.c | 121 +++++++++++++++++++++++------- drivers/clk/samsung/clk-exynos5x-subcmu.c | 2 + drivers/soc/samsung/pm_domains.c | 2 + 4 files changed, 100 insertions(+), 26 deletions(-) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Krzysztof Kozlowski diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index ef8900bc077f..f70b3f66be89 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o +obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5x-subcmu.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 45d34f601e9e..dbf4b5243987 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -19,6 +19,7 @@ #include "clk.h" #include "clk-cpu.h" +#include "clk-exynos5x-subcmu.h" #define APLL_LOCK 0x0 #define APLL_CON0 0x100 @@ -863,7 +864,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), - DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3), @@ -912,8 +912,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), - /* Mfc Block */ - DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), /* PCM */ DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), @@ -932,8 +930,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), /* GSCL Block */ - DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", - DIV2_RATIO0, 4, 2), DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), /* MSCL Block */ @@ -1190,8 +1186,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", GATE_TOP_SCLK_GSCL, 7, 0, 0), - GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), - GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", GATE_IP_GSCL0, 4, 0, 0), GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", @@ -1205,10 +1199,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE_IP_GSCL1, 3, 0, 0), GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", GATE_IP_GSCL1, 4, 0, 0), - GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", - GATE_IP_GSCL1, 6, 0, 0), - GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", - GATE_IP_GSCL1, 7, 0, 0), GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", @@ -1227,18 +1217,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", GATE_IP_MSCL, 10, 0, 0), - GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), - GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), - GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), - GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), - GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), - GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", - GATE_IP_DISP1, 7, 0, 0), - GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", - GATE_IP_DISP1, 8, 0, 0), - GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", - GATE_IP_DISP1, 9, 0, 0), - /* ISP */ GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), @@ -1255,11 +1233,98 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), + GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), +}; + +static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { + DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), +}; + +static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { + GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), + GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), + GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), + GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), + GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), + GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", + GATE_IP_DISP1, 7, 0, 0), + GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", + GATE_IP_DISP1, 8, 0, 0), + GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", + GATE_IP_DISP1, 9, 0, 0), +}; + +static struct samsung_clk_ext_reg_dump exynos_5x_disp_suspend_regs[] = { + { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ + { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ + { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ + { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ + { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ +}; + +static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { + DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", + DIV2_RATIO0, 4, 2), +}; + +static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { + GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), + GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), + GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", + GATE_IP_GSCL1, 6, 0, 0), + GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", + GATE_IP_GSCL1, 7, 0, 0), +}; + +static struct samsung_clk_ext_reg_dump exynos_5x_gsc_suspend_regs[] = { + { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ + { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ + { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ + { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ +}; + +static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { + DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), +}; + +static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), +}; - GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), +static struct samsung_clk_ext_reg_dump exynos_5x_mfc_suspend_regs[] = { + { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ + { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ + { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ +}; + +static const struct samsung_5x_subcmu_info exynos_5x_subcmus[] = { + { + .div_clks = exynos5x_disp_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), + .gate_clks = exynos5x_disp_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), + .suspend_regs = exynos_5x_disp_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos_5x_disp_suspend_regs), + .pd_name = "DISP", + }, { + .div_clks = exynos5x_gsc_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), + .gate_clks = exynos5x_gsc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), + .suspend_regs = exynos_5x_gsc_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos_5x_gsc_suspend_regs), + .pd_name = "GSC", + }, { + .div_clks = exynos5x_mfc_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), + .gate_clks = exynos5x_mfc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), + .suspend_regs = exynos_5x_mfc_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos_5x_mfc_suspend_regs), + .pd_name = "MFC", + }, }; static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { @@ -1472,6 +1537,8 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); exynos5420_clk_sleep_init(); + samsung_clk_subcmus_init(ctx, ARRAY_SIZE(exynos_5x_subcmus), + exynos_5x_subcmus); samsung_clk_of_add_provider(np, ctx); } @@ -1480,10 +1547,12 @@ static void __init exynos5420_clk_init(struct device_node *np) { exynos5x_clk_init(np, EXYNOS5420); } -CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); +CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", + exynos5420_clk_init); static void __init exynos5800_clk_init(struct device_node *np) { exynos5x_clk_init(np, EXYNOS5800); } -CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init); +CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", + exynos5800_clk_init); diff --git a/drivers/clk/samsung/clk-exynos5x-subcmu.c b/drivers/clk/samsung/clk-exynos5x-subcmu.c index 9ff6d5d17f57..256473b83264 100644 --- a/drivers/clk/samsung/clk-exynos5x-subcmu.c +++ b/drivers/clk/samsung/clk-exynos5x-subcmu.c @@ -159,6 +159,8 @@ static int __init exynos5x_clk_probe(struct platform_device *pdev) } static const struct of_device_id exynos5x_clk_of_match[] = { + { .compatible = "samsung,exynos5420-clock", }, + { .compatible = "samsung,exynos5800-clock", }, { }, }; diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index cef30bdf19b1..f2d6d7a09c16 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -148,6 +148,8 @@ static __init const char *exynos_get_domain_name(struct device_node *node) } static const char *soc_force_no_clk[] = { + "samsung,exynos5420-clock", + "samsung,exynos5800-clock", }; static __init int exynos4_pm_init_power_domain(void)