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Thu, 9 Nov 2017 08:12:16 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20171109081216eucas1p1cdd0e8c43689b11db9d8d76f72556b18~1XKo7UB6i0994509945eucas1p1P; Thu, 9 Nov 2017 08:12:16 +0000 (GMT) X-AuditID: cbfec7f4-f79ab6d000003290-31-5a040de04d3f Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 5A.05.18832.0ED040A5; Thu, 9 Nov 2017 08:12:16 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OZ5001YG5G1B580@eusync3.samsung.com>; Thu, 09 Nov 2017 08:12:16 +0000 (GMT) From: Marek Szyprowski To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Inki Dae , Seung-Woo Kim , Andrzej Hajda , Bartlomiej Zolnierkiewicz , Tobias Jakobi , Krzysztof Kozlowski , Sylwester Nawrocki , Andrzej Pietrasiewicz , Hoegeun Kwon Subject: [PATCH v6 7/8] ARM: dts: exynos: Add mem-2-mem Scaler devices Date: Thu, 09 Nov 2017 09:11:55 +0100 Message-id: <20171109081156.7111-8-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171109081156.7111-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGIsWRmVeSWpSXmKPExsWy7djPc7oPeFmiDI5N1bC4te4cq8Wsl+0s FhtnrGe1uPL1PZvF++VdbBaT7k9gsTh/fgO7xYzz+5gs1h65y25x+E07q8WMyS/ZLNpWf2B1 4PHYtKqTzeN+93Emj3/H2D36tqxi9Pi8SS6ANYrLJiU1J7MstUjfLoErY8GBQ8wFzZIVK+7M ZmpgvCzcxcjJISFgInGz5xIrhC0mceHeerYuRi4OIYGljBI9e2cxQTifGSWeXNvHAtOx5+V+ ZojEMkaJlVN2QVU1MEnM3rgBrIpNwFCi620XG4gtIuAm0XR4JitIEbPALmaJF5Nfs3cxcnAI AyVuTLIEqWERUJXo/tcE1ssrYCPxf845Joht8hLvF9xnBLE5BWwlbi+4C7ZZQmALm8TeC+8Y IYpcJDa92gT1hLDEq+Nb2CFsGYnOjoNQg/oZJZpatSHsGYwS597yQtjWEoePXwTrZRbgk5i0 bTozyG0SArwSHW1CECUeEovu74L63lFiS+N+qIcnMEocnNbHNIFRegEjwypGkdTS4tz01GIT veLE3OLSvHS95PzcTYzA2D797/iXHYyLj1kdYhTgYFTi4X2xijlKiDWxrLgy9xCjBAezkgiv yFugEG9KYmVValF+fFFpTmrxIUZpDhYlcV7bqLZIIYH0xJLU7NTUgtQimCwTB6dUA+MS75OS 9/bsOdIgO7+gVaZRZIFU6OS5W4s+KvM8OflgVaLu/qUuhwv3BQpXrw3lPudxe7Wss6AuZ/Pj 438jdwed/rW15vePqtKd6aucwq8aXeC9c2yd0/JM88nb/vA9Oibla7xLq13ne4NsiPn92s6w jJI1u90OTHS8Fbih1cru14uZy1UfRycosRRnJBpqMRcVJwIAmQdWlukCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrFLMWRmVeSWpSXmKPExsVy+t/xq7oPeFmiDE4c4LO4te4cq8Wsl+0s FhtnrGe1uPL1PZvF++VdbBaT7k9gsTh/fgO7xYzz+5gs1h65y25x+E07q8WMyS/ZLNpWf2B1 4PHYtKqTzeN+93Emj3/H2D36tqxi9Pi8SS6ANYrLJiU1J7MstUjfLoErY8GBQ8wFzZIVK+7M ZmpgvCzcxcjJISFgIrHn5X5mCFtM4sK99WxdjFwcQgJLGCV+rF/CCuE0MUn83/KSDaSKTcBQ outtF5gtIuAm0XR4JiuIzSywj1liY5t3FyMHhzBQ/MYkS5Awi4CqRPe/JhYQm1fARuL/nHNM EMvkJd4vuM8IYnMK2ErcXnAX7AghoJrORXfYJzDyLmBkWMUoklpanJueW2yoV5yYW1yal66X nJ+7iREYgtuO/dy8g/HSxuBDjAIcjEo8vC9WMUcJsSaWFVfmHmKU4GBWEuEVeQsU4k1JrKxK LcqPLyrNSS0+xCjNwaIkztu7Z3WkkEB6YklqdmpqQWoRTJaJg1OqgTHG5turehZ961uT8vdW tyw7etsuRaY/acWPlWsXBJVKp/Eu8jK7kK1d0mHLvWGGi771Hg5Gr8tnOtKsPmkwPrOa5Lv9 X37G87XStfeM1i5pORfu863ybNBvyYnODEeL37HoHZb/17V4yYsCvkM29v+vBh0r+HvHNv8Q u/7KV4ezenb5hW9d36HEUpyRaKjFXFScCAC7mxS4PQIAAA== X-CMS-MailID: 20171109081216eucas1p1cdd0e8c43689b11db9d8d76f72556b18 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20171109081216eucas1p1cdd0e8c43689b11db9d8d76f72556b18 X-RootMTR: 20171109081216eucas1p1cdd0e8c43689b11db9d8d76f72556b18 References: <20171109081156.7111-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Andrzej Pietrasiewicz There are 3 scaler devices in Exynos5420 SoCs, all are a part of MSCL power domain. MSCL power domain and SYSMMU controllers (two per each scaler device) have been already added to exynos5420.dtsi earlier, so bind them to newly added devices. Signed-off-by: Andrzej Pietrasiewicz Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos5420.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- 2.14.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8aa2cc7aa125..0e742ab81e62 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -678,6 +678,35 @@ iommus = <&sysmmu_gscl1>; }; + scaler_0: scaler@12800000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12800000 0x1294>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL0>; + clock-names = "mscl"; + power-domains = <&msc_pd>; + iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>; + }; + + scaler_1: scaler@12810000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12810000 0x1294>; + interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL1>; + clock-names = "mscl"; + power-domains = <&msc_pd>; + iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>; + }; + scaler_2: scaler@12820000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12820000 0x1294>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL2>; + clock-names = "mscl"; + power-domains = <&msc_pd>; + iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>; + }; + jpeg_0: jpeg@11F50000 { compatible = "samsung,exynos5420-jpeg"; reg = <0x11F50000 0x1000>; @@ -812,6 +841,7 @@ interrupts = <22 4>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; @@ -821,6 +851,7 @@ interrupts = ; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; @@ -830,6 +861,7 @@ interrupts = ; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; @@ -840,6 +872,7 @@ interrupts = <27 2>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; @@ -850,6 +883,7 @@ interrupts = <22 6>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; @@ -860,6 +894,7 @@ interrupts = <19 6>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + power-domains = <&msc_pd>; #iommu-cells = <0>; };