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Mon, 02 Oct 2017 11:48:26 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH 3/4] ARM: dts: exynos: Add Exynos4412 ISP clock controller Date: Mon, 02 Oct 2017 12:47:58 +0200 Message-id: <20171002104759.25944-4-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171002104759.25944-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrBIsWRmVeSWpSXmKPExsWy7djP87pVkpciDSZ91bDYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6Mp6f+Mhcc1avYs7yDpYFxjkoXIyeHhICJxJa/j1ggbDGJC/fWs3UxcnEI CSxllHj64iczSEJI4DOjxL1GPZiGT99fQRUtY5SY+esZlNPAJDGjdQMTSBWbgKFE19suNhBb RMBB4vOn14wgRcwCbUwSZw/sBysSFvCSWLT1EmsXIwcHi4CqxLQbsSBhXgFbiQ09HVAnyUu8 X3CfEcTmFLCTaD6wkgVkjoRAB5vEnH0nmSGKXCROHFgOZQtLvDq+hR3ClpG4PLkbalA/o0RT qzaEPYNR4txbXgjbWuLw8YusIDazAJ/EpG3TmUHukRDglehoE4Io8ZB4Mr8ParyjRMu3FhaI hycySkz7uYl9AqP0AkaGVYwiqaXFuempxUZ6xYm5xaV56XrJ+bmbGIHxefrf8Y87GN+fsDrE KMDBqMTDq2FyMVKINbGsuDL3EKMEB7OSCC8v26VIId6UxMqq1KL8+KLSnNTiQ4zSHCxK4ry2 UW2RQgLpiSWp2ampBalFMFkmDk6pBkbhdUktH84Ht/73eLjo/fnrHaIvX6++Ucb5hys2MmVH mhq7eF23nmSA4eTf3kyrqh9FaaVY5xz8tTvt6hxRiTVh81ZrPi5/sTHzzWWfuXaP0hwZ9j1a mRdbcXHL4h/+Yc8cZ9Snf+2I4xGKqF7JqvFS4oRq+KqUN3fKPDd/OKn/vev470sWaUpKLMUZ iYZazEXFiQDT1sNmywIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplluLIzCtJLcpLzFFi42I5/e/4Vd0qyUuRBid7uSw2zljPanH9y3NW i0n3J7BYnD+/gd3iY889VosZ5/cxWaw9cpfd4vCbdlYHDo9NqzrZPPq2rGL0+LxJLoA5issm JTUnsyy1SN8ugSvj6am/zAVH9Sr2LO9gaWCco9LFyMkhIWAi8en7KzYIW0ziwr31QDYXh5DA EkaJ03N3gCWEBJqYJCZ8jwex2QQMJbredoHFRQQcJD5/es0I0sAs0MEksWfvQ7CEsICXxKKt l1i7GDk4WARUJabdiAUJ8wrYSmzo6WCBWCYv8X7BfUYQm1PATqL5wEoWiF22EnPXbmafwMi7 gJFhFaNIamlxbnpusZFecWJucWleul5yfu4mRmAgbTv2c8sOxq53wYcYBTgYlXh4NUwuRgqx JpYVV+YeYpTgYFYS4eVluxQpxJuSWFmVWpQfX1Sak1p8iFGag0VJnLd3z+pIIYH0xJLU7NTU gtQimCwTB6dUA6PGzgaRpdI7lI2uavgc6fm9PiaW38fi6NLTkVymqYra6msLbC9+EW3SSnBd 69rW082ho7rzWaHF5bsugU7HJv+sUfS2S8v+/MLFwEqpafnWzUvqrD1kc67+5z4RcTH7kffy iG9O85qutOT+l2CdE3ukQP1ijYYVn0bg0b1cwTMrchwsup3zlFiKMxINtZiLihMBSrFZAyAC AAA= X-CMS-MailID: 20171002104826eucas1p15c0d0d9038e5b1119fd244ecab502d35 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-CMS-RootMailID: 20171002104826eucas1p15c0d0d9038e5b1119fd244ecab502d35 X-RootMTR: 20171002104826eucas1p15c0d0d9038e5b1119fd244ecab502d35 References: <20171002104759.25944-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos4412 ISP clock controller is located in the SOC area, which belongs to ISP power domain. This patch instantiates a separate clock driver for those clocks, updates all clients of ISP clocks and ensures that the driver is properly integrated in ISP power domin. This finally solves all the mysterious freezes in accessing ISP clocks when ISP power domain is disabled. Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos4412.dtsi | 71 ++++++++++++++++++++++++--------------- 1 file changed, 44 insertions(+), 27 deletions(-) -- 2.14.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7ff03a7e8fb9..2a2f1e596672 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -191,10 +191,19 @@ clock: clock-controller@10030000 { compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x20000>; + reg = <0x10030000 0x18000>; #clock-cells = <1>; }; + isp_clock: clock-controller@10048000 { + compatible = "samsung,exynos4412-isp-clock"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + power-domains = <&pd_isp>; + clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>; + clock-names = "aclk200", "aclk400_mcuisp"; + }; + mct@10050000 { compatible = "samsung,exynos4412-mct"; reg = <0x10050000 0x800>; @@ -257,7 +266,7 @@ reg = <0x12390000 0x1000>; interrupts = ; power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE0>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; clock-names = "flite"; iommus = <&sysmmu_fimc_lite0>; status = "disabled"; @@ -268,7 +277,7 @@ reg = <0x123A0000 0x1000>; interrupts = ; power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE1>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; clock-names = "flite"; iommus = <&sysmmu_fimc_lite1>; status = "disabled"; @@ -280,29 +289,35 @@ interrupts = , ; power-domains = <&pd_isp>; - clocks = <&clock CLK_FIMC_LITE0>, - <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, - <&clock CLK_PPMUISPMX>, + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE1>, + <&isp_clock CLK_ISP_PPMUISPX>, + <&isp_clock CLK_ISP_PPMUISPMX>, + <&isp_clock CLK_ISP_FIMC_ISP>, + <&isp_clock CLK_ISP_FIMC_DRC>, + <&isp_clock CLK_ISP_FIMC_FD>, + <&isp_clock CLK_ISP_MCUISP>, + <&isp_clock CLK_ISP_GICISP>, + <&isp_clock CLK_ISP_MCUCTL_ISP>, + <&isp_clock CLK_ISP_PWM_ISP>, + <&isp_clock CLK_ISP_DIV_ISP0>, + <&isp_clock CLK_ISP_DIV_ISP1>, + <&isp_clock CLK_ISP_DIV_MCUISP0>, + <&isp_clock CLK_ISP_DIV_MCUISP1>, <&clock CLK_MOUT_MPLL_USER_T>, - <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, - <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, - <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>, - <&clock CLK_PWM_ISP>, - <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>, - <&clock CLK_DIV_MCUISP0>, - <&clock CLK_DIV_MCUISP1>, - <&clock CLK_UART_ISP_SCLK>, - <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, + <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>, - <&clock CLK_DIV_ACLK400_MCUISP>; + <&clock CLK_DIV_ACLK200>, + <&clock CLK_DIV_ACLK400_MCUISP>, + <&clock CLK_UART_ISP_SCLK>; clock-names = "lite0", "lite1", "ppmuispx", - "ppmuispmx", "mpll", "isp", + "ppmuispmx", "isp", "drc", "fd", "mcuisp", "gicisp", "mcuctl_isp", "pwm_isp", "ispdiv0", "ispdiv1", "mcuispdiv0", - "mcuispdiv1", "uart", "aclk200", - "div_aclk200", "aclk400mcuisp", - "div_aclk400mcuisp"; + "mcuispdiv1", "mpll", "aclk200", + "aclk400mcuisp", "div_aclk200", + "div_aclk400mcuisp", "uart"; iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; iommu-names = "isp", "drc", "fd", "mcuctl"; @@ -318,7 +333,7 @@ i2c1_isp: i2c-isp@12140000 { compatible = "samsung,exynos4212-i2c-isp"; reg = <0x12140000 0x100>; - clocks = <&clock CLK_I2C1_ISP>; + clocks = <&isp_clock CLK_ISP_I2C1_ISP>; clock-names = "i2c_isp"; #address-cells = <1>; #size-cells = <0>; @@ -355,7 +370,7 @@ interrupts = <16 2>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_ISP>; + clocks = <&isp_clock CLK_ISP_SMMU_ISP>; #iommu-cells = <0>; }; @@ -366,7 +381,7 @@ interrupts = <16 3>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_DRC>; + clocks = <&isp_clock CLK_ISP_SMMU_DRC>; #iommu-cells = <0>; }; @@ -377,7 +392,7 @@ interrupts = <16 4>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_FD>; + clocks = <&isp_clock CLK_ISP_SMMU_FD>; #iommu-cells = <0>; }; @@ -388,7 +403,7 @@ interrupts = <16 5>; power-domains = <&pd_isp>; clock-names = "sysmmu"; - clocks = <&clock CLK_SMMU_ISPCX>; + clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; #iommu-cells = <0>; }; @@ -399,7 +414,8 @@ interrupts = <16 0>; power-domains = <&pd_isp>; clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>; + clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE0>; #iommu-cells = <0>; }; @@ -410,7 +426,8 @@ interrupts = <16 1>; power-domains = <&pd_isp>; clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; + clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, + <&isp_clock CLK_ISP_FIMC_LITE1>; #iommu-cells = <0>; };