From patchwork Wed Oct 12 13:17:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 77555 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp443106qge; Wed, 12 Oct 2016 06:18:05 -0700 (PDT) X-Received: by 10.98.57.140 with SMTP id u12mr1682938pfj.127.1476278285756; Wed, 12 Oct 2016 06:18:05 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id lm5si7764477pab.26.2016.10.12.06.18.05; Wed, 12 Oct 2016 06:18:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933262AbcJLNSE (ORCPT + 4 others); Wed, 12 Oct 2016 09:18:04 -0400 Received: from mail.kernel.org ([198.145.29.136]:59660 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932266AbcJLNSD (ORCPT ); Wed, 12 Oct 2016 09:18:03 -0400 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E8C2D203AA; Wed, 12 Oct 2016 13:18:01 +0000 (UTC) Received: from localhost (unknown [69.71.4.155]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C569C20211; Wed, 12 Oct 2016 13:18:00 +0000 (UTC) Subject: [PATCH v2 02/10] PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll() To: Joao Pinto , Pratyush Anand From: Bjorn Helgaas Cc: Jingoo Han , Krzysztof Kozlowski , Kukjin Kim , linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Date: Wed, 12 Oct 2016 08:17:59 -0500 Message-ID: <20161012131758.26443.96419.stgit@bhelgaas-glaptop2.roam.corp.google.com> In-Reply-To: <20161012131616.26443.89407.stgit@bhelgaas-glaptop2.roam.corp.google.com> References: <20161012131616.26443.89407.stgit@bhelgaas-glaptop2.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, NML_ADSP_CUSTOM_MED,UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Kishon Vijay Abraham I dw_pcie_readl_unroll() and dw_pcie_writel_unroll() duplicate what dw_pcie_readl_rc() and dw_pcie_writel_rc() already do, so call them directly. [bhelgaas: reworked into patch series] Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-designware.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index b58f078..7ce4f75 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -161,10 +161,7 @@ static inline u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); - if (pp->ops->readl_rc) - return pp->ops->readl_rc(pp, pp->dbi_base + offset + reg); - - return readl(pp->dbi_base + offset + reg); + return dw_pcie_readl_rc(pp, offset + reg); } static inline void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, @@ -172,10 +169,7 @@ static inline void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); - if (pp->ops->writel_rc) - pp->ops->writel_rc(pp, val, pp->dbi_base + offset + reg); - else - writel(val, pp->dbi_base + offset + reg); + dw_pcie_writel_rc(pp, val, offset + reg); } static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,