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Fri, 29 Sep 2017 08:33:04 +0100 (BST) From: Marek Szyprowski To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Inki Dae , Seung-Woo Kim , Andrzej Hajda , Bartlomiej Zolnierkiewicz , Tobias Jakobi , Krzysztof Kozlowski , Sylwester Nawrocki , Andrzej Pietrasiewicz , linux-clk@vger.kernel.org Subject: [PATCH v2 8/9] drivers: clk: samsung: Fix m2m scaler clock on Exynos542x Date: Fri, 29 Sep 2017 09:32:53 +0200 Message-id: <1506670374-15689-9-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1506670374-15689-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKIsWRmVeSWpSXmKPExsWy7djP87oG389GGlw/qWdxa905VotZL9tZ LDbOWM9qceXrezaLSfcnsFicP7+B3eJjzz1Wixnn9zFZrD1yl93i8Jt2IHfySzaLttUfWB14 PDat6mTzuN99nMnj3zF2j74tqxg9Pm+SC2CN4rJJSc3JLEst0rdL4Mr48OYde8FcrorTD/az NTA+5uhi5OSQEDCR+Nd0nwnCFpO4cG89WxcjF4eQwFJGicVt81khnM+MEr92/2WC6biwoo0d IrGMUeL3zMNQLQ1MEo+WnGEBqWITMJToetvFBmKLCLhJNB2eCTaKWWANs8TRN1MZQRLCAsES nUungNksAqoSC6c2sIPYvAIeEjdOb2WDWCcncfLYZFYQm1PAU+Ja71J2iPgGNome74kQtovE /qnroc4Tlnh1fAtUjYzE5cndLBB2P6NEU6s2hD2DUeLcW14I21ri8PGLYPOZBfgkJm2bztzF yAEU55XoaBOCKPGQmHhuBytE2FFiz3YLiH/nMEqsae9hmcAovYCRYRWjSGppcW56arGJXnFi bnFpXrpecn7uJkZgZJ/+d/zLDsbFx6wOMQpwMCrx8N6QOxspxJpYVlyZe4hRgoNZSYT33Ueg EG9KYmVValF+fFFpTmrxIUZpDhYlcV7bqLZIIYH0xJLU7NTUgtQimCwTB6dUA+OS5yuXCudO 7n1ad5JbYsYraYtFOsZHFh1/1HHr7eKpFt76z3u+mj1/F/9Nd/v+jtAjV//m/vJM2395Ni// y/vvXcPaY/Y0ndzPMet9mmOsjvO6aWpcM5lcvbL9A+On15kZ/7ny1HzxhQ9X7zpX7y5ZsW/p SoXX9kks9QbPFrFZhFgmT1CYrPJWiaU4I9FQi7moOBEAZC4x0OgCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrDLMWRmVeSWpSXmKPExsVy+t/xy7oG389GGrTv4bW4te4cq8Wsl+0s FhtnrGe1uPL1PZvFpPsTWCzOn9/AbvGx5x6rxYzz+5gs1h65y25x+E07kDv5JZtF2+oPrA48 HptWdbJ53O8+zuTx7xi7R9+WVYwenzfJBbBGcdmkpOZklqUW6dslcGV8ePOOvWAuV8XpB/vZ Ghgfc3QxcnJICJhIXFjRxg5hi0lcuLeerYuRi0NIYAmjxNcvT5khnCYmietTOlhBqtgEDCW6 3naxgdgiAm4STYdnsoIUMQusY5bYsaSXCSQhLBAs0bl0CiOIzSKgKrFwagPYCl4BD4kbp7ey QayTkzh5bDLYUE4BT4lrvUvBaoSAan5d/8I8gZF3ASPDKkaR1NLi3PTcYiO94sTc4tK8dL3k /NxNjMAw3Hbs55YdjF3vgg8xCnAwKvHw3pA7GynEmlhWXJl7iFGCg1lJhHf+N6AQb0piZVVq UX58UWlOavEhRmkOFiVx3t49qyOFBNITS1KzU1MLUotgskwcnFINjIqW4cefrZvDo3lD7fbx jMJ1z5r8m83mPCqdnMT08EN+374X9hvfNrz/fuKJ2PrYH3G2s7PfObx63heZu67x0uwW37Lz qU1Rbz65pd47kvpdIeDXqYu6lhYtor/ZTMUWXNsUlru0lDNFnvmc5iPGDS9F4n9XvGvSLnVj i274F5j35BtD6G1WCyWW4oxEQy3mouJEAEvymOM/AgAA X-CMS-MailID: 20170929073304eucas1p2825d0ccd64de3b39409b6767660b5543 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-CMS-RootMailID: 20170929073304eucas1p2825d0ccd64de3b39409b6767660b5543 X-RootMTR: 20170929073304eucas1p2825d0ccd64de3b39409b6767660b5543 References: <1506670374-15689-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Andrzej Pietrasiewicz TOP "aclk400_mscl" clock should be kept enabled all the time to allow proper access to power management control for MSC power domain and devices that are a part of it. This change is required for scaler to work properly after domain power on/off sequence. Fixes: 318fa46cc60d ("clk/samsung: exynos542x: mark some clocks as critical") Signed-off-by: Andrzej Pietrasiewicz Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos5420.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 25601967d1cd..038701a2af4c 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -998,7 +998,7 @@ static void __init exynos5420_clk_sleep_init(void) {} GATE(0, "aclk400_isp", "mout_user_aclk400_isp", GATE_BUS_TOP, 16, 0, 0), GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", - GATE_BUS_TOP, 17, 0, 0), + GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",