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Thu, 26 Jan 2017 12:38:05 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH v2 2/3] clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates Date: Thu, 26 Jan 2017 13:37:53 +0100 Message-id: <1485434274-6579-3-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1485434274-6579-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJIsWRmVeSWpSXmKPExsWy7djPc7rr3nZGGNxeJWixccZ6VovrX56z Wpw/v4HdYsb5fUwWa4/cZbc4/Kad1YHNY9OqTjaPvi2rGD0+b5ILYI7isklJzcksSy3St0vg yuha0MlesISjovHgbqYGxu9sXYycHBICJhLXHx5mh7DFJC7cWw8U5+IQEljKKDH/8g8o5zOj xPrj51lgOh4t3ccMkVjGKLH2zk8op4FJYs7B6cwgVWwChhJdb7vAdogIqEp8blvADlLELPCU UeLe4hYmkISwQIzE2v4GRhCbBajo7IzTYHFeAXeJ2asfMUGsk5M4eWwyK4jNKeAhse7TJajD 77NJtH3n7mLkALJlJTYdYIYIu0js3HGaFcIWlnh1fAvUbzISnR0HoUb2M0o0tWpD2DMYJc69 5YWwrSUOH78I1ssswCcxaRvILyDjeSU62oQgSoAu2LiFEcJ2lFjSPxlsvJDAbEaJtjfmExhl FjAyrGIUSS0tzk1PLTbRK07MLS7NS9dLzs/dxAiM0NP/jn/Zwbj4mNUhRgEORiUe3gM7OiKE WBPLiitzDzFKcDArifAufNkZIcSbklhZlVqUH19UmpNafIhRmoNFSZx3z4Ir4UIC6Yklqdmp qQWpRTBZJg5OqQbGENGVcxPXq639u8ikvSnN2ui7yOf+X8JP/nrFsXGH28+cfWTxrE23Vt3N Pbwm0HM770mxl60tNdvk5UPTVvu8nd36cOJEZ5WDnoxiCvyLjF643LwWU7zjSGpF3GJDLc/r i9UrfbZ967kiI1loc63gq/F2Nr4Kn6AXXT9MLR4pWH0qPdO15YmfEktxRqKhFnNRcSIAJnS1 N8wCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrFLMWRmVeSWpSXmKPExsVy+t/xa7pv33ZGGFw9bWyxccZ6VovrX56z Wpw/v4HdYsb5fUwWa4/cZbc4/Kad1YHNY9OqTjaPvi2rGD0+b5ILYI5ys8lITUxJLVJIzUvO T8nMS7dVCg1x07VQUshLzE21VYrQ9Q0JUlIoS8wpBfKMDNCAg3OAe7CSvl2CW0bXgk72giUc FY0HdzM1MH5n62Lk5JAQMJF4tHQfM4QtJnHh3nqgOBeHkMASRonZ1y4yQzhNTBLXtu9jBKli EzCU6HrbBdYtIqAq8bltATtIEbPAc0aJ97v7WUASwgIxEmv7G8AaWICKzs44zQRi8wq4S8xe /YgJYp2cxMljk1lBbE4BD4l1ny4BDeUA2uYusWMt/wRG3gWMDKsYRVJLi3PTc4sN9YoTc4tL 89L1kvNzNzECw3XbsZ+bdzBe2hh8iFGAg1GJh/fAjo4IIdbEsuLK3EOMEhzMSiK8C192Rgjx piRWVqUW5ccXleakFh9iNAW6aSKzlGhyPjCW8kriDU0MzS0NjYwtLMyNjJTEeUs+XAkXEkhP LEnNTk0tSC2C6WPi4JRqYLTPe+YiWnlTqJLxWIofr0/MOufFm07xr9Csl47YMG9WwOSp6tKX X2r9/n9gZ5LSkZUnfR/v3mM04Quv23muFX/mRDmtsXpy9O5COUOX1XfPz3Y1qQ5sXRb101ll y6mq1sRfU6/nvLLSjZ2z7/7Be1O2X3+7vKMtdHHGEuVjs9v3Sb359jnOVV1PiaU4I9FQi7mo OBEAAJZxw20CAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170126123805eucas1p2b95ab23660b7a6631ab7f639ebaff0fc X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170126123805eucas1p2b95ab23660b7a6631ab7f639ebaff0fc X-RootMTR: 20170126123805eucas1p2b95ab23660b7a6631ab7f639ebaff0fc References: <1485434274-6579-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Default clock configuration applied by the bootloader for TM2 and TM2e boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure such configuration for those boards with 'assigned-clocks*' properties, parameters for those two additional rates are needed. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos5433.c | 2 ++ 1 file changed, 2 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Chanwoo Choi diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 6ee91ae875c3..11343a597093 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -739,7 +739,9 @@ PLL_35XX_RATE(350000000U, 350, 6, 2), PLL_35XX_RATE(333000000U, 222, 4, 2), PLL_35XX_RATE(300000000U, 500, 5, 3), + PLL_35XX_RATE(278000000U, 556, 6, 3), PLL_35XX_RATE(266000000U, 532, 6, 3), + PLL_35XX_RATE(250000000U, 500, 6, 3), PLL_35XX_RATE(200000000U, 400, 6, 3), PLL_35XX_RATE(166000000U, 332, 6, 3), PLL_35XX_RATE(160000000U, 320, 6, 3),