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Wed, 25 Jan 2017 11:56:01 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi , Inki Dae Subject: [PATCH 7/8] arm64: dts: exynos: Add FSYS power domain to Exynos5433 SoC Date: Wed, 25 Jan 2017 12:55:41 +0100 Message-id: <1485345342-3273-8-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1485345342-3273-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrEIsWRmVeSWpSXmKPExsWy7djP87ohkzoiDFa2WFtsnLGe1eL6l+es FpPuT2CxOH9+A7vF594jjBYzzu9jslh75C67xeE37awOHB6bVnWyefRtWcXo8XmTXABzFJdN SmpOZllqkb5dAlfGid+7mAvmi1V8Pn2RrYFxmmAXIyeHhICJxP6+ZewQtpjEhXvr2boYuTiE BJYxSvzcdJodwvnMKDFxwwZWmI6uxeuZQWywqg/P5CHsBiaJc7/iQGw2AUOJrrddbCC2iIC9 xO0ny8AGMQu0MUnsutUGNkhYIEji4M8PYINYBFQlzl59yAJi8wq4Sxz4cZARYpmcxMljk8Hq OQU8JLqe9jNBxN+zSeydI9HFyAFky0psOsAMEXaR6F16COobYYlXx7dA2TISnR0HoVr7GSWa WrUh7BmMEufe8kLY1hKHj18EW8UswCcxadt0ZojxvBIdbUIQJR4S/5pXQI10lOiZ+ZwREj6z GSXudt1jn8Aos4CRYRWjSGppcW56arGhXnFibnFpXrpecn7uJkZgzJ7+d/z9DsanzSGHGAU4 GJV4eF+ktEcIsSaWFVfmHmKU4GBWEuFdMrEjQog3JbGyKrUoP76oNCe1+BCjNAeLkjjv3gVX woUE0hNLUrNTUwtSi2CyTBycUg2MAcHT3lj8PpM4QUgsWyG/5v2+Czeq81abV3Xbyy8zKD2e tKJ1wtQnN/1KDGwXr7l8WvYr442f9ee1gnPO/pv24Mn9ta4GievljqwolpiUFx+QKeQSNX3+ B+Y7U6v2rs8xsbBVv77RRCIw1bf1bcPdqT/WHDdPnvuwSdppzcpboYpVzy13vpCRUmIpzkg0 1GIuKk4EAOC20cbVAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCLMWRmVeSWpSXmKPExsVy+t/xK7oTJ3VEGHxbxGGxccZ6VovrX56z Wky6P4HF4vz5DewWn3uPMFrMOL+PyWLtkbvsFofftLM6cHhsWtXJ5tG3ZRWjx+dNcgHMUW42 GamJKalFCql5yfkpmXnptkqhIW66FkoKeYm5qbZKEbq+IUFKCmWJOaVAnpEBGnBwDnAPVtK3 S3DLOPF7F3PBfLGKz6cvsjUwThPsYuTkkBAwkehavJ4ZwhaTuHBvPVsXIxeHkMASRon9i5+w QDhNTBLvTm5nAqliEzCU6HrbxQZiiwjYS9x+sowdpIhZoINJ4t+dFqAEB4ewQIDE1juaIDUs AqoSZ68+ZAGxeQXcJQ78OMgIsU1O4uSxyawgNqeAh0TX036w+UJANVNvrmWZwMi7gJFhFaNI amlxbnpusaFecWJucWleul5yfu4mRmAIbzv2c/MOxksbgw8xCnAwKvHwTkhqjxBiTSwrrsw9 xCjBwawkwuvQ0hEhxJuSWFmVWpQfX1Sak1p8iNEU6KiJzFKiyfnA+MoriTc0MTS3NDQytrAw NzJSEuct+XAlXEggPbEkNTs1tSC1CKaPiYNTqoHRubzF9MSMtP6DE47M6VqfUXghsHS1szfP Q622s3aTjvDNtWPJ8zmxqOvQHF2rdY/tm8Kmhb78fcdvq6zLCbZvkzfURjf8rlw3RYv3l7pU cVFQ67LaaxkxZ18atvvmm/k/sV11w5Fp/dYjn41uy+t4LUpbd9mLy/t88Kdvb+eauHEtNpuw 4X6YEktxRqKhFnNRcSIADu9c3ncCAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170125115601eucas1p1e90bdf34ae4cb71f4d7c58232fff1a13 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170125115601eucas1p1e90bdf34ae4cb71f4d7c58232fff1a13 X-RootMTR: 20170125115601eucas1p1e90bdf34ae4cb71f4d7c58232fff1a13 References: <1485345342-3273-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch adds support for FSYS power domain to Exynos 5433 SoCs, which contains following devices: a clock controller, a pin controller, three MSHC controllers, two DWC USB 3.0 controllers and their PHYs. Signed-off-by: Marek Szyprowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 24fc3b46cc40..0e18e9aeb4ce 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -330,6 +330,7 @@ <&cmu_top CLK_SCLK_MMC0_FSYS>, <&cmu_top CLK_SCLK_USBHOST30_FSYS>, <&cmu_top CLK_SCLK_USBDRD30_FSYS>; + power-domains = <&pd_fsys>; }; cmu_g2d: clock-controller@12460000 { @@ -560,6 +561,12 @@ #power-domain-cells = <0>; }; + pd_fsys: fsys-power-domain@105c40e0 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c40e0 0x20>; + #power-domain-cells = <0>; + }; + tmu_atlas0: tmu@10060000 { compatible = "samsung,exynos5433-tmu"; reg = <0x10060000 0x200>; @@ -697,6 +704,7 @@ compatible = "samsung,exynos5433-pinctrl"; reg = <0x15690000 0x1000>; interrupts = ; + power-domains = <&pd_fsys>; }; pinctrl_imem: pinctrl@11090000 { @@ -1417,6 +1425,7 @@ clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&cmu_fsys CLK_SCLK_USBDRD30>; clock-names = "usbdrd30", "usbdrd30_susp_clk"; + power-domains = <&pd_fsys>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -1442,6 +1451,7 @@ "itp"; #phy-cells = <1>; samsung,pmu-syscon = <&pmu_system_controller>; + power-domains = <&pd_fsys>; status = "disabled"; }; @@ -1456,6 +1466,7 @@ "itp"; #phy-cells = <1>; samsung,pmu-syscon = <&pmu_system_controller>; + power-domains = <&pd_fsys>; status = "disabled"; }; @@ -1464,6 +1475,7 @@ clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&cmu_fsys CLK_SCLK_USBHOST30>; clock-names = "usbdrd30", "usbdrd30_susp_clk"; + power-domains = <&pd_fsys>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -1488,6 +1500,7 @@ <&cmu_fsys CLK_SCLK_MMC0>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; + power-domains = <&pd_fsys>; status = "disabled"; }; @@ -1501,6 +1514,7 @@ <&cmu_fsys CLK_SCLK_MMC1>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; + power-domains = <&pd_fsys>; status = "disabled"; }; @@ -1514,6 +1528,7 @@ <&cmu_fsys CLK_SCLK_MMC2>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; + power-domains = <&pd_fsys>; status = "disabled"; };