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Thu, 17 Nov 2016 08:58:11 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Seung-Woo Kim , Chanwoo Choi Subject: [PATCH v2 3/5] arm64: dts: exynos: Move FSYS CMU configuration from Exynos5433 dtsi to TM2 dts Date: Thu, 17 Nov 2016 09:57:59 +0100 Message-id: <1479373081-11586-4-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1479373081-11586-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrDIsWRmVeSWpSXmKPExsWy7djP87oqhboRBse0LDbOWM9qcf3Lc1aL 8+c3sFvMOL+PyWLtkbvsFofftLNazJj8ks2B3WPTqk42j74tqxg9Pm+SC2CO4rJJSc3JLEst 0rdL4MqYPucue0GnUsXfT9INjK9kuhg5OSQETCQOTrnCCmGLSVy4t56ti5GLQ0hgKaPEru5X 7BDOZ0aJz3/mscJ03FzWzAyRWMYosb75DVRVA5PEsecTGEGq2AQMJbredrGB2CICqhKf2xaA FTEL9DJJbLlzAywhLJApsez/TTCbBajo15YGdhCbV8BDoqPhHDPEOjmJk8cmA63m4OAU8JTo 66mECD9mk3izJB8kLCEgK7HpAFS1i8TC3i5GCFtY4tXxLewQtoxEZ8dBJgi7n1GiqVUbwp7B KHHuLS+EbS1x+PhFsCeZBfgkJm2bzgwxnleio00IosRDYvm7f2wQtqPEm6/HWSBen8Mo8Wny cfYJjDILGBlWMYqklhbnpqcWG+kVJ+YWl+al6yXn525iBMbp6X/HP+5gfH/C6hCjAAejEg/v gXydCCHWxLLiytxDjBIczEoivG2ZuhFCvCmJlVWpRfnxRaU5qcWHGKU5WJTEefcsuBIuJJCe WJKanZpakFoEk2Xi4JRqYJyyeW/GZofdb98tj7qnxhR+M2vFLl1V7+4vfsvV+NYeTj6zmsWu LWDv5D3cK041NX6O331deKpuyRTOFYyfUy0Fl338ejp3Rt3Ss+eXVLA/35zUyxqay5AtNcnh wvzV6vHtP79JnnpZoTlHiVFDbfVBVwHG75GSW+evKPauCLpgvaOeTSVvdZsSS3FGoqEWc1Fx IgAu5DczzwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLLMWRmVeSWpSXmKPExsVy+t/xK7qahboRBucnmlpsnLGe1eL6l+es FufPb2C3mHF+H5PF2iN32S0Ov2lntZgx+SWbA7vHplWdbB59W1YxenzeJBfAHOVmk5GamJJa pJCal5yfkpmXbqsUGuKma6GkkJeYm2qrFKHrGxKkpFCWmFMK5BkZoAEH5wD3YCV9uwS3jOlz 7rIXdCpV/P0k3cD4SqaLkZNDQsBE4uayZmYIW0ziwr31bCC2kMASRonOg2pdjFxAdhOTxJqn N5lAEmwChhJdb7vAikQEVCU+ty1gByliFuhnkjgzewsjSEJYIFNi2f+bYEUsQEW/tjSwg9i8 Ah4SHQ3noLbJSZw8Npm1i5GDg1PAU6KvpxJisYfE5b/PmScw8i5gZFjFKJJaWpybnltsqFec mFtcmpeul5yfu4kRGLTbjv3cvIPx0sbgQ4wCHIxKPLwSRToRQqyJZcWVuYcYJTiYlUR42zJ1 I4R4UxIrq1KL8uOLSnNSiw8xmgLdNJFZSjQ5HxhReSXxhiaG5paGRsYWFuZGRkrivCUfroQL CaQnlqRmp6YWpBbB9DFxcEo1MIqE8grK7dGxnVNa9XOWR9e5ABaZTcJ+QXrTRN7yXnP6uGOO /iPL+5cZelN/ff/IN2PyWjUnh0ncOxtiLx14Oql2bf25EtM/+utP9wrb5j1OnLTh2c6Jfzue PVThmP3p1oScwLXnhO/99bYMeqlrmRew+tGdCSyJs6V476lIfH+6t6Pd3fX4/i1KLMUZiYZa zEXFiQDWbqQWcAIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20161117085811eucas1p1b1fcdd080d43f46ef44558ba0e62e4d3 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20161117085811eucas1p1b1fcdd080d43f46ef44558ba0e62e4d3 X-RootMTR: 20161117085811eucas1p1b1fcdd080d43f46ef44558ba0e62e4d3 References: <1479373081-11586-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is a board specific item. Signed-off-by: Marek Szyprowski Reviewed-by: Sylwester Nawrocki Reviewed-by: Chanwoo Choi --- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 23 ++++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 28 --------------------------- 2 files changed, 23 insertions(+), 28 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index d3fa03fd0230..0f93e795ab2e 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -165,6 +165,29 @@ }; }; +&cmu_fsys { + assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, + <&cmu_top CLK_MOUT_SCLK_USBHOST30>, + <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, + <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>, + <&cmu_top CLK_DIV_SCLK_USBDRD30>, + <&cmu_top CLK_DIV_SCLK_USBHOST30>; + assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>, + <&cmu_top CLK_MOUT_BUS_PLL_USER>, + <&cmu_top CLK_SCLK_USBDRD30_FSYS>, + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; + assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, + <66700000>, <66700000>; +}; + &cpu0 { cpu-supply = <&buck3_reg>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index a80eb4c22c7a..ab2935253cca 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1134,14 +1134,6 @@ clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&cmu_fsys CLK_SCLK_USBDRD30>; clock-names = "usbdrd30", "usbdrd30_susp_clk"; - assigned-clocks = - <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, - <&cmu_top CLK_MOUT_SCLK_USBDRD30>, - <&cmu_top CLK_DIV_SCLK_USBDRD30>; - assigned-clock-parents = - <&cmu_top CLK_SCLK_USBDRD30_FSYS>, - <&cmu_top CLK_MOUT_BUS_PLL_USER>; - assigned-clock-rates = <0>, <0>, <66700000>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -1165,12 +1157,6 @@ <&cmu_fsys CLK_SCLK_USBDRD30>; clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; - assigned-clocks = - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>; - assigned-clock-parents = - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>; #phy-cells = <1>; samsung,pmu-syscon = <&pmu_system_controller>; status = "disabled"; @@ -1185,12 +1171,6 @@ <&cmu_fsys CLK_SCLK_USBHOST30>; clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; - assigned-clocks = - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>; - assigned-clock-parents = - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; #phy-cells = <1>; samsung,pmu-syscon = <&pmu_system_controller>; status = "disabled"; @@ -1201,14 +1181,6 @@ clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&cmu_fsys CLK_SCLK_USBHOST30>; clock-names = "usbdrd30", "usbdrd30_susp_clk"; - assigned-clocks = - <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, - <&cmu_top CLK_MOUT_SCLK_USBHOST30>, - <&cmu_top CLK_DIV_SCLK_USBHOST30>; - assigned-clock-parents = - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, - <&cmu_top CLK_MOUT_BUS_PLL_USER>; - assigned-clock-rates = <0>, <0>, <66700000>; #address-cells = <1>; #size-cells = <1>; ranges;