From patchwork Wed Dec 9 08:07:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 57933 Delivered-To: patch@linaro.org Received: by 10.112.147.194 with SMTP id tm2csp519755lbb; Wed, 9 Dec 2015 00:07:51 -0800 (PST) X-Received: by 10.98.0.138 with SMTP id 132mr11090040pfa.131.1449648471042; Wed, 09 Dec 2015 00:07:51 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 29si10954945pfq.225.2015.12.09.00.07.50; Wed, 09 Dec 2015 00:07:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751395AbbLIIHt (ORCPT + 4 others); Wed, 9 Dec 2015 03:07:49 -0500 Received: from mailout2.w1.samsung.com ([210.118.77.12]:40903 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751354AbbLIIHt (ORCPT ); Wed, 9 Dec 2015 03:07:49 -0500 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZ200DP1ZWY9390@mailout2.w1.samsung.com>; Wed, 09 Dec 2015 08:07:46 +0000 (GMT) X-AuditID: cbfec7f5-f79b16d000005389-f3-5667e15220cc Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 0F.60.21385.251E7665; Wed, 9 Dec 2015 08:07:46 +0000 (GMT) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZ200C8UZWUMN80@eusync2.samsung.com>; Wed, 09 Dec 2015 08:07:46 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Tomasz Figa , Mike Turquette , Krzysztof Kozlowski , Kukjin Kim Subject: [PATCH v2 2/2] ARM: dts: exynos542x: add GSCL block parent clock management to pm domain Date: Wed, 09 Dec 2015 09:07:35 +0100 Message-id: <1449648455-18279-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 In-reply-to: <5667B38E.5020207@samsung.com> References: <5667B38E.5020207@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprGLMWRmVeSWpSXmKPExsVy+t/xK7pBD9PDDK6fUrB4/cLQov/xa2aL y7vmsFnMOL+PyWLtkbvsFhdPuVocftPOarFq1x9GBw6P9zda2T12zrrL7rFpVSebR9+WVYwe nzfJBbBGcdmkpOZklqUW6dslcGW8bmtmK+hlr/jc+IW9gfELaxcjB4eEgInElcfVXYycQKaY xIV769m6GLk4hASWMkos6W9lhHCamCSa1rSwgFSxCRhKdL3tYgOxRQScJRqmNjKB2MwC/xkl Fr12BLGFBZIlTh68yApiswioSlw88psRxOYV8JA48eYHM8Q2OYn/L1eA9XIKaEs8n9LKDmIL CWhJHJvwhmUCI+8CRoZVjKKppckFxUnpuUZ6xYm5xaV56XrJ+bmbGCGh9XUH49JjVocYBTgY lXh4K5zSw4RYE8uKK3MPMUpwMCuJ8BaeBwrxpiRWVqUW5ccXleakFh9ilOZgURLnnbnrfYiQ QHpiSWp2ampBahFMlomDU6qBcQuzp+SBS7oL9hiqlJvckFTz9PhgW9D12yXIptdDadLWOsZP z2/8ffUh/MmFELb7wXGTCmxzn+WELGnMCmvm/y/r5y+bOO88L/ubKq0tk00XKCb+k+d54/I7 nEngVVRxxq41p0sZ4+fyKUrvXXiZTaD59O2QVuaNd+tXFxee6DXIuXPwSxCbEktxRqKhFnNR cSIAr4f6DCkCAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add support for restoring GScaler parent clocks configuration when GSCL power domain is turned on. Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos5420.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 1.9.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 1b3d6c7..5d00c18 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -252,8 +252,10 @@ compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; #power-domain-cells = <0>; - clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; - clock-names = "asb0", "asb1"; + clocks = <&clock CLK_FIN_PLL>, + <&clock CLK_MOUT_USER_ACLK300_GSCL>, + <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; + clock-names = "oscclk", "clk0", "asb0", "asb1"; }; isp_pd: power-domain@10044020 {