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[209.132.180.67]) by mx.google.com with ESMTP id cp4si9552444pad.96.2014.09.22.05.17.29 for ; Mon, 22 Sep 2014 05:17:30 -0700 (PDT) Received-SPF: none (google.com: linux-samsung-soc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753560AbaIVMR3 (ORCPT + 6 others); Mon, 22 Sep 2014 08:17:29 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:63611 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753491AbaIVMR2 (ORCPT ); Mon, 22 Sep 2014 08:17:28 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NCA00IO0Y9TK910@mailout3.w1.samsung.com> for linux-samsung-soc@vger.kernel.org; Mon, 22 Sep 2014 13:20:17 +0100 (BST) X-AuditID: cbfec7f5-b7f776d000003e54-fc-54201355735d Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 71.87.15956.55310245; Mon, 22 Sep 2014 13:17:25 +0100 (BST) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync1.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0NCA00EUJY4XNG30@eusync1.samsung.com>; Mon, 22 Sep 2014 13:17:25 +0100 (BST) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Tomasz Figa Subject: [PATCH] clk: exynos4: fix g3d clocks Date: Mon, 22 Sep 2014 14:17:12 +0200 Message-id: <1411388232-6271-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKJMWRmVeSWpSXmKPExsVy+t/xy7qhwgohBhtWGVnMOL+PyWLtkbvs FofftLNarNr1h9GBxWPnrLvsHn1bVjF6fN4kF8AcxWWTkpqTWZZapG+XwJWxadFOxoK5fBXn 501hbWDs4uli5OSQEDCR6Jl6lwnCFpO4cG89WxcjF4eQwFJGiXNLvkM5fUwSaz5MZwapYhMw lOh628UGYosIqEp8blvADlLELNDKKLH65WYgh4NDWEBX4sVLF5AaFqCaA++3s4PYvALuEne7 2tghtslJ/H+5gmkCI/cCRoZVjKKppckFxUnpuUZ6xYm5xaV56XrJ+bmbGCFe/7qDcekxq0OM AhyMSjy8P1rkQ4RYE8uKK3MPMUpwMCuJ8PryKIQI8aYkVlalFuXHF5XmpBYfYmTi4JRqYLxQ uF/LZM+65+ukn395kDZlvdr8/PxPzPne3nMaq1ap7mz8xJFRad3Ck36/4aDXrXnqMZPOXWpR i+gVDQiWZP5ot/Liotp9sqIvkm8KNb09v2pfp2gOt+yqrQqt1hp3/fc1bFkXseewum2D2KSy D8aC+unheRNtb5y3Sa55v2TbR++PL73bJyuxFGckGmoxFxUnAgBnyC+O2AEAAA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: m.szyprowski@samsung.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked g3d gate clock bits for this purpose and didn't provide real g3d clock at all. This patch fixes this issue by adding proper definition for g3d clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos4.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index ac163d7f5bc3..111be8469e3d 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -733,8 +733,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), - DIV_F(0, "div_g3d", "mout_g3d", DIV_G3D, 0, 4, - CLK_SET_RATE_PARENT, 0), + DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4), DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), @@ -857,8 +856,7 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = { 0), GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), - GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, - CLK_SET_RATE_PARENT, 0), + GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0), GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0), GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),