From patchwork Wed Jun 18 11:31:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 32130 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ve0-f197.google.com (mail-ve0-f197.google.com [209.85.128.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id DF38E206A0 for ; Wed, 18 Jun 2014 11:31:18 +0000 (UTC) Received: by mail-ve0-f197.google.com with SMTP id jz11sf2304631veb.4 for ; Wed, 18 Jun 2014 04:31:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:sender:precedence:list-id:x-original-sender :x-original-authentication-results:mailing-list:list-post:list-help :list-archive:list-unsubscribe; bh=zfScDLXpHOvTKnY9+mZOFSoNDRzEEMO4dO0klpjMHaA=; b=kUly87lAg+6BOqcDj8Gk9oHC9It4528HoDS2kx4HOLOUGK9KB3kzjIM+Eo6HbX7Zdj jIkN5N2qo8xP3568F5N2gv+g645yyPGCM5qfzMFWHkuoPtAK6RQAuRNm7PTzz6svqTIb YGI5LCNvwD2pPfpooxOOuS78Ni5fCvS8omTBXJZizYSyKYtPgDU8Uml0BWBo+fLgagMQ 9Gq4ZyDymm3IBUSJ9Wbp8tA/zlPCo7PpTC6yJDNAq8Nv11xnxOiZILY/+Q0OxhpaJJ2W IFEGNu30FLMVF92lVbTLdvKbcHLN00KBWVP7GZWSsq7Qq6fo+4Av8CQj5/EFtWKmPmew +TLg== X-Gm-Message-State: ALoCoQkxmDBSUuMxgPSzQHT1lg3O934H7JOUN7m5/8BfQA3xETP51skZwXPbQAqXqAGhteGph/Ch X-Received: by 10.236.81.99 with SMTP id l63mr2658962yhe.3.1403091078731; Wed, 18 Jun 2014 04:31:18 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.80.81 with SMTP id b75ls55101qgd.34.gmail; Wed, 18 Jun 2014 04:31:18 -0700 (PDT) X-Received: by 10.52.185.39 with SMTP id ez7mr22463070vdc.7.1403091078657; Wed, 18 Jun 2014 04:31:18 -0700 (PDT) Received: from mail-ve0-x22f.google.com (mail-ve0-x22f.google.com [2607:f8b0:400c:c01::22f]) by mx.google.com with ESMTPS id ub7si741903veb.10.2014.06.18.04.31.18 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 18 Jun 2014 04:31:18 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c01::22f as permitted sender) client-ip=2607:f8b0:400c:c01::22f; Received: by mail-ve0-f175.google.com with SMTP id jx11so645273veb.20 for ; Wed, 18 Jun 2014 04:31:18 -0700 (PDT) X-Received: by 10.52.244.138 with SMTP id xg10mr22004999vdc.1.1403091078568; Wed, 18 Jun 2014 04:31:18 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.54.6 with SMTP id vs6csp277165vcb; Wed, 18 Jun 2014 04:31:18 -0700 (PDT) X-Received: by 10.68.213.74 with SMTP id nq10mr1927955pbc.4.1403091077829; Wed, 18 Jun 2014 04:31:17 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id xs3si1845206pbb.247.2014.06.18.04.31.16; Wed, 18 Jun 2014 04:31:17 -0700 (PDT) Received-SPF: none (google.com: linux-samsung-soc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965876AbaFRLbP (ORCPT + 8 others); Wed, 18 Jun 2014 07:31:15 -0400 Received: from mail-pd0-f181.google.com ([209.85.192.181]:44590 "EHLO mail-pd0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933182AbaFRLbO (ORCPT ); Wed, 18 Jun 2014 07:31:14 -0400 Received: by mail-pd0-f181.google.com with SMTP id v10so613440pde.12 for ; Wed, 18 Jun 2014 04:31:13 -0700 (PDT) X-Received: by 10.66.120.201 with SMTP id le9mr1809237pab.98.1403091073860; Wed, 18 Jun 2014 04:31:13 -0700 (PDT) Received: from localhost.localdomain ([14.140.216.146]) by mx.google.com with ESMTPSA id ix7sm3020118pbd.36.2014.06.18.04.31.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Jun 2014 04:31:13 -0700 (PDT) From: Amit Daniel Kachhap To: linux-samsung-soc@vger.kernel.org, Kukjin Kim , Daniel Lezcano , Thomas Gleixner Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, David Riley , Doug Anderson , Tomasz Figa Subject: [PATCH] clocksource: exynos-mct: Register the timer for stable udelay Date: Wed, 18 Jun 2014 17:01:00 +0530 Message-Id: <1403091060-5054-1-git-send-email-amit.daniel@samsung.com> X-Mailer: git-send-email 1.9.1 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Original-Sender: amit.daniel@samsung.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c01::22f as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=neutral (body hash did not verify) header.i=@ Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch register the exynos mct clocksource as the current timer as it has constant clock rate. This will generate correct udelay for the exynos platform and avoid using unnecessary calibrated jiffies. This change have been tested on exynos5420 based board. Signed-off-by: Amit Daniel Kachhap --- Patches from David Riley confirmed that udelay is broken in exynos5420. Link to those patches are, 1) https://patchwork.kernel.org/patch/4344911/ 2) https://patchwork.kernel.org/patch/4344881/ drivers/clocksource/exynos_mct.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 8d64200..57cb3dc 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -198,10 +198,21 @@ static u64 notrace exynos4_read_sched_clock(void) return exynos4_frc_read(&mct_frc); } +static struct delay_timer exynos4_delay_timer; + +static unsigned long exynos4_read_current_timer(void) +{ + return exynos4_frc_read(&mct_frc); +} + static void __init exynos4_clocksource_init(void) { exynos4_mct_frc_start(0, 0); + exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; + exynos4_delay_timer.freq = clk_rate; + register_current_timer_delay(&exynos4_delay_timer); + if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name);