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Fri, 16 Jun 2023 19:03:06 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%7]) with mapi id 15.20.6477.037; Fri, 16 Jun 2023 19:03:06 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Christophe Leroy , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kevin Tian , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Russell King , linuxppc-dev@lists.ozlabs.org, Matthias Brugger , Matthew Rosato , Michael Ellerman , Nicholas Piggin , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Dmitry Osipenko , Marek Szyprowski , Nicolin Chen , Niklas Schnelle , Steven Price , Thierry Reding Subject: [PATCH v4 14/25] iommu/msm: Implement an IDENTITY domain Date: Fri, 16 Jun 2023 16:02:43 -0300 Message-Id: <14-v4-874277bde66e+1a9f6-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v4-874277bde66e+1a9f6-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR20CA0049.namprd20.prod.outlook.com (2603:10b6:208:235::18) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|SJ1PR12MB6051:EE_ X-MS-Office365-Filtering-Correlation-Id: 8b1c951e-1edc-4e03-015a-08db6e9c4be0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fL2fYieiYy0mEntm6Za9cRiowu1XVA/+FtlDUiDyaRr92vcSZtHs1/wE7vl1EVo+tcb96zkVy4SWbPWtcWtStD6qDFSbCZBb9dyvCpWytlx/tyK1w8YOz6cgKQSMBIbBw6+KsvwDN8DruNSbb0N0uHQg8CSLgVGPs3sxlL6eO79w+h85pkgpXhfQRt/vtDkathQAQ57NpgiRhCxf3LeCZle1gQDR4B2PuNT6ESgOyfQw1Rk8lhcFCKmO0fxEthJLRumE165ODcf+yEVv/QIPtfx9Grb0p+SBBIt6wGFAnRvo7nIW3Z6IgCEj3MEeyFjokYkJb/2RnwOfOW6atcBV+d2qir47eiTSm5NtWekOKsRI++h5KANqLpxemnbdFcRT3nTs3j9eNMiNZPeKtaDFKPTjb3i8ewU2lFz9niQB0AE6BstRIcccXfAHkyldiXib26QT4Hut9HCl2SSzQ6+u++W0ElYsyBIrZ7yKQke/QCDu4axPaGZaObCHXA9B6COjTSjgolPejaQ+Dequd4QHrx+0mEyVoTHrdeTzB25/Mt/h7jPN4zRftL/PgdAHE33UyLGtbA2WE0MeeWKAbKPBOC5Ao9EbnIptGnfZ9tFZnicbTJh5SEpOO7dJWytewoaIV50UiRY2I0E33s0XQKlhjWgaYo2FFoguwxSZmrX8q3dzrFIAOjz2/L2HPzJjsrVxbRgoAKTfvNSMRhVyfWqWOyAl2WbHbqZCRW72XnZl8a0d85XFK/nrQ5NXCnwDzUA5oY6H0HOimLLtIiv6YXHcGPWFa1GNVCMTYKtQcq+CtM4Hk2Xu5aGQKKnpBAkBdpyxEPpFaD2kiJckXXWfLeMpLy/YoIfgvm5xgOTSYHU9xWIhgtFda2rYH7fa3vU+0GDfy+rb1GaMmNhbOQKuqkm/i4l+Of2Tm9fNC/HWEU0lq6TLaZPf73VS9MY/nFLfae6pytwALHNW2Y0cKC408O+Kun+ZDZveH9xvRRGun2dFx88svL36DhEyCzxayHP+gCYxEQEgM/0Mk7uQ5QgsDw55bd5DxUczqq7XlYnuSknQgBFagczuDSyQgNh8RYZP7B8US1VzFK8Bo9eyvAGpJZzZOkXAuprm5OTGN1GYfKwP4ZBjTJtDytpTzs4idzOWqHSnon2m1P3hm+BK6y2LlVPW6UEuwK8yeOb+UDNlSNfUzsbV1jFMKaz4nxOBdSBQDxFt+j1eGXZwNuztJY/8Xnxh44QZE+UDoPpZB7UU9tDcDiTDdl78Q5oJH7Zd2CxjCTPjMbb7DKBWed3rjzUcBJufSO0741D0zskPo9NN45ZnuOWS2wCBeNsITa5QmswTc4tbnZJ2wCe6EQBx09IIR0srimaeYbr2jhm/TTnHVASxtiSqOBwrYq+96MJEwDppW15scBlNJ+3As+mCCEFsbHwRS1UNdhmd9MIkXgFTPzTv4KFe+f9QnlhOgdZUvJaZ+FHdS4ffo9n9YFuGbej6PexJOCJ1PSrAdAFhWXaBaLrstSUFqbEKBEazifOCNEqPt4GVdzviROw4Znm695Ub42uZf4rOdlukHGc7h7RK6j3bjsoO3hIOOA8Uvbv6s9CiGC68 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8b1c951e-1edc-4e03-015a-08db6e9c4be0 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2023 19:02:57.1430 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XtUi2J+xpHy+60QXEs3ROS20LkFeg1pZTqozuCSTffnsDda6RkbvJfTZ+h4Pfl3S X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6051 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org What msm does during omap_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Signed-off-by: Jason Gunthorpe --- drivers/iommu/msm_iommu.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 79d89bad5132b7..26ed81cfeee897 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -443,15 +443,20 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) return ret; } -static void msm_iommu_set_platform_dma(struct device *dev) +static int msm_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct msm_priv *priv = to_msm_priv(domain); + struct msm_priv *priv; unsigned long flags; struct msm_iommu_dev *iommu; struct msm_iommu_ctx_dev *master; - int ret; + int ret = 0; + if (domain == identity_domain || !domain) + return 0; + + priv = to_msm_priv(domain); free_io_pgtable_ops(priv->iop); spin_lock_irqsave(&msm_iommu_lock, flags); @@ -468,8 +473,18 @@ static void msm_iommu_set_platform_dma(struct device *dev) } fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); + return ret; } +static struct iommu_domain_ops msm_iommu_identity_ops = { + .attach_dev = msm_iommu_identity_attach, +}; + +static struct iommu_domain msm_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &msm_iommu_identity_ops, +}; + static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t pa, size_t pgsize, size_t pgcount, int prot, gfp_t gfp, size_t *mapped) @@ -675,10 +690,10 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) } static struct iommu_ops msm_iommu_ops = { + .identity_domain = &msm_iommu_identity_domain, .domain_alloc = msm_iommu_domain_alloc, .probe_device = msm_iommu_probe_device, .device_group = generic_device_group, - .set_platform_dma_ops = msm_iommu_set_platform_dma, .pgsize_bitmap = MSM_IOMMU_PGSIZES, .of_xlate = qcom_iommu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) {