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[209.132.180.67]) by mx.google.com with ESMTP id ps1si4047587pbc.336.2014.04.24.22.45.06; Thu, 24 Apr 2014 22:45:06 -0700 (PDT) Received-SPF: none (google.com: linux-samsung-soc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751802AbaDYFod (ORCPT + 9 others); Fri, 25 Apr 2014 01:44:33 -0400 Received: from mail-pb0-f52.google.com ([209.85.160.52]:38392 "EHLO mail-pb0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751807AbaDYFob (ORCPT ); Fri, 25 Apr 2014 01:44:31 -0400 Received: by mail-pb0-f52.google.com with SMTP id rq2so2784446pbb.25 for ; Thu, 24 Apr 2014 22:44:30 -0700 (PDT) X-Received: by 10.68.234.2 with SMTP id ua2mr5209491pbc.81.1398404669939; Thu, 24 Apr 2014 22:44:29 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id vg1sm13134641pbc.44.2014.04.24.22.44.27 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 24 Apr 2014 22:44:29 -0700 (PDT) From: Chander Kashyap To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, tomasz.figa@gmail.com, Chander Kashyap , Chander Kashyap Subject: [PATCH] arm: exynos: add generic function to calculate cpu number Date: Fri, 25 Apr 2014 11:14:13 +0530 Message-Id: <1398404653-14407-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: chander.kashyap@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The address of cpu power registers in pmu is based on cpu number offsets. This function calculate the same. This is essentially required in case of multicluster SoC's e.g Exynos5420. Signed-off-by: Chander Kashyap Signed-off-by: Chander Kashyap --- arch/arm/mach-exynos/regs-pmu.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 4f6a256..217da2e 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -313,4 +313,13 @@ #define EXYNOS5_OPTION_USE_RETENTION (1 << 4) +#include +#define MAX_CPUS_IN_CLUSTER 4 + +static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr) +{ + return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER) + + MPIDR_AFFINITY_LEVEL(mpidr, 0)); +} + #endif /* __ASM_ARCH_REGS_PMU_H */