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[209.132.180.67]) by mx.google.com with ESMTP id zt8si22758150pbc.273.2014.04.22.05.25.17; Tue, 22 Apr 2014 05:25:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932233AbaDVMZQ (ORCPT + 8 others); Tue, 22 Apr 2014 08:25:16 -0400 Received: from mail-pd0-f177.google.com ([209.85.192.177]:47978 "EHLO mail-pd0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932195AbaDVMZP (ORCPT ); Tue, 22 Apr 2014 08:25:15 -0400 Received: by mail-pd0-f177.google.com with SMTP id y10so4809418pdj.36 for ; Tue, 22 Apr 2014 05:25:15 -0700 (PDT) X-Received: by 10.67.14.231 with SMTP id fj7mr9452705pad.115.1398169515274; Tue, 22 Apr 2014 05:25:15 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id pr4sm84617389pbb.53.2014.04.22.05.25.12 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 22 Apr 2014 05:25:14 -0700 (PDT) From: Chander Kashyap To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, tomasz.figa@gmail.com, Chander Kashyap , Chander Kashyap Subject: [PATCH v5] arm: exynos: generalize power register address calculation Date: Tue, 22 Apr 2014 17:55:01 +0530 Message-Id: <1398169501-7251-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398068989-9905-1-git-send-email-chander.kashyap@linaro.org> References: <1398068989-9905-1-git-send-email-chander.kashyap@linaro.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: chander.kashyap@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Currently status/configuration power register values are hard-coded for cpu1. Make it generic so that it is useful for SoC's with more than two cpus. Signed-off-by: Chander Kashyap Signed-off-by: Chander Kashyap --- changes in v5: 1. Fix typo: enynos_pmu_cpunr -> exynos_pmu_cpunr changes in v4: 1: Dropped changes in platsmp.c and hotplug.c as those are taken care by Tomasz Patches. 2. Converted ENYNOS_PMU_CPUNR macro to static inline function changes in v3: 1. Move cpunr calculation to a macro 2. Changed printk format specifier from unsigned hex to unsigned decimal Changes in v2: 1. Used existing macros for clusterid and cpuid calculation arch/arm/mach-exynos/regs-pmu.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 4f6a256..f39e78c 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -105,8 +105,13 @@ #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) -#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) -#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084) +#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) +#define S5P_ARM_CORE0_STATUS S5P_PMUREG(0x2004) + +#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \ + (S5P_ARM_CORE0_CONFIGURATION + 0x80 * (_cpunr)) +#define S5P_ARM_CORE_STATUS(_cpunr) \ + (S5P_ARM_CORE0_STATUS + 0x80 * (_cpunr)) #define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) #define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) @@ -313,4 +318,13 @@ #define EXYNOS5_OPTION_USE_RETENTION (1 << 4) +#include +#define MAX_CPUS_IN_CLUSTER 4 + +static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr) +{ + return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER) + + MPIDR_AFFINITY_LEVEL(mpidr, 0)); +} + #endif /* __ASM_ARCH_REGS_PMU_H */