From patchwork Tue Apr 15 07:38:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 28393 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pb0-f71.google.com (mail-pb0-f71.google.com [209.85.160.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id A2DAF2036D for ; Tue, 15 Apr 2014 07:38:37 +0000 (UTC) Received: by mail-pb0-f71.google.com with SMTP id up15sf35009529pbc.10 for ; Tue, 15 Apr 2014 00:38:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=kl3IU78Zv5ChT9P6mdmHKS9Cqmg4obaLtGjO+XhRjls=; b=WomUk6vBUzJR5CWvHXUAMYlQpif9Qw4r/LhBHi+P5y0GouRgGhfY3ILy5VAyFNq7bN tZFpg9yA0x7eWTtCwVE0w7fOcg20m0bHNxflQDcim7NDgMrIj+9ntsgVSjvKvHjS2XBK DFH+eHis6+5iQG2LypvHZh9f3xP0VcqnWk90lhJyxv0XnsE/Cw0nZnj8D+qBgit39GQf HJfJS6+0zAPpSJR6XfZ0CrwlcyIQw3EbxqGIxyt0Mi4us7EdxEUU4Gy7QW9Titg4+Bzg 8Prl7HEt7z+hAhCzS+IFEE1EvPgBSDrnAkT6Cr4yxK89lq/1SoMP1MvZkGNO08Ri7trZ 4hXg== X-Gm-Message-State: ALoCoQkCTImjO6WgobSg+ChtadMitDiZFKRGzy9U1NghCblO25jwq8AikKT1RKemdeBd3zA5Rear X-Received: by 10.68.230.193 with SMTP id ta1mr157332pbc.6.1397547516909; Tue, 15 Apr 2014 00:38:36 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.98.68 with SMTP id n62ls26445qge.28.gmail; Tue, 15 Apr 2014 00:38:36 -0700 (PDT) X-Received: by 10.220.175.70 with SMTP id w6mr95725vcz.72.1397547516809; Tue, 15 Apr 2014 00:38:36 -0700 (PDT) Received: from mail-ve0-f179.google.com (mail-ve0-f179.google.com [209.85.128.179]) by mx.google.com with ESMTPS id wj8si3255023vcb.92.2014.04.15.00.38.36 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 15 Apr 2014 00:38:36 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.179 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.179; Received: by mail-ve0-f179.google.com with SMTP id db12so8924535veb.10 for ; Tue, 15 Apr 2014 00:38:36 -0700 (PDT) X-Received: by 10.220.103.141 with SMTP id k13mr78766vco.25.1397547516726; Tue, 15 Apr 2014 00:38:36 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp210006vcb; Tue, 15 Apr 2014 00:38:36 -0700 (PDT) X-Received: by 10.66.166.47 with SMTP id zd15mr381441pab.0.1397547515577; Tue, 15 Apr 2014 00:38:35 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id sf3si10262969pac.452.2014.04.15.00.38.34; Tue, 15 Apr 2014 00:38:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750938AbaDOHie (ORCPT + 8 others); Tue, 15 Apr 2014 03:38:34 -0400 Received: from mail-pb0-f41.google.com ([209.85.160.41]:61158 "EHLO mail-pb0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750855AbaDOHid (ORCPT ); Tue, 15 Apr 2014 03:38:33 -0400 Received: by mail-pb0-f41.google.com with SMTP id jt11so9169697pbb.14 for ; Tue, 15 Apr 2014 00:38:33 -0700 (PDT) X-Received: by 10.68.221.42 with SMTP id qb10mr213495pbc.65.1397547513122; Tue, 15 Apr 2014 00:38:33 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id kc9sm38409416pbc.25.2014.04.15.00.38.30 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 15 Apr 2014 00:38:32 -0700 (PDT) From: Chander Kashyap To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: kgene.kim@samsung.com, tomasz.figa@gmail.com, Chander Kashyap Subject: [PATCH] arm: exynos: generalize power register address calculation Date: Tue, 15 Apr 2014 13:08:18 +0530 Message-Id: <1397547498-21729-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: chander.kashyap@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.179 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Currently status/configuration power register values are hard-coded for cpu1. Make it generic so that it is useful for SoC's with more than two cpus. Signed-off-by: Chander Kashyap --- changes in v3: 1. Move cpunr calculation to a macro 2. Changed printk format specifier from unsigned hex to unsigned decimal Changes in v2: 1. Used existing macros for clusterid and cpuid calculation arch/arm/mach-exynos/hotplug.c | 7 ++++--- arch/arm/mach-exynos/platsmp.c | 13 +++++++------ arch/arm/mach-exynos/regs-pmu.h | 15 +++++++++++++-- 3 files changed, 24 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c index 5eead53..9f74be2 100644 --- a/arch/arm/mach-exynos/hotplug.c +++ b/arch/arm/mach-exynos/hotplug.c @@ -92,11 +92,12 @@ static inline void cpu_leave_lowpower(void) static inline void platform_do_lowpower(unsigned int cpu, int *spurious) { + unsigned int cpunr = ENYNOS_PMU_CPUNR(cpu_logical_map(cpu)); for (;;) { - /* make cpu1 to be turned off at next WFI command */ - if (cpu == 1) - __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION); + /* make cpu to be turned off at next WFI command */ + if (cpu) + __raw_writel(0, S5P_ARM_CORE_CONFIGURATION(cpunr)); /* * here's the WFI diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 03e5e9f..d9c182f 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -90,7 +90,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; unsigned long phys_cpu = cpu_logical_map(cpu); - + unsigned int cpunr = ENYNOS_PMU_CPUNR(cpu_logical_map(cpu)); /* * Set synchronisation state between this boot processor * and the secondary one @@ -107,14 +107,15 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) */ write_pen_release(phys_cpu); - if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) { + if (!(__raw_readl(S5P_ARM_CORE_STATUS(cpunr)) + & S5P_CORE_LOCAL_PWR_EN)) { __raw_writel(S5P_CORE_LOCAL_PWR_EN, - S5P_ARM_CORE1_CONFIGURATION); + S5P_ARM_CORE_CONFIGURATION(cpunr)); timeout = 10; - /* wait max 10 ms until cpu1 is on */ - while ((__raw_readl(S5P_ARM_CORE1_STATUS) + /* wait max 10 ms until secondary cpu is on */ + while ((__raw_readl(S5P_ARM_CORE_STATUS(cpunr)) & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) { if (timeout-- == 0) break; @@ -123,7 +124,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) } if (timeout == 0) { - printk(KERN_ERR "cpu1 power enable failed"); + pr_err("cpu%u power enable failed", cpu); spin_unlock(&boot_lock); return -ETIMEDOUT; } diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 4f6a256..0de6df4 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -105,8 +105,13 @@ #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) -#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) -#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084) +#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) +#define S5P_ARM_CORE0_STATUS S5P_PMUREG(0x2004) + +#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \ + (S5P_ARM_CORE0_CONFIGURATION + 0x80 * (_cpunr)) +#define S5P_ARM_CORE_STATUS(_cpunr) \ + (S5P_ARM_CORE0_STATUS + 0x80 * (_cpunr)) #define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) #define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) @@ -313,4 +318,10 @@ #define EXYNOS5_OPTION_USE_RETENTION (1 << 4) +#include +#define MAX_CPUS_IN_CLUSTER 4 +#define ENYNOS_PMU_CPUNR(mpidr) \ + ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER) \ + + MPIDR_AFFINITY_LEVEL(mpidr, 0)); + #endif /* __ASM_ARCH_REGS_PMU_H */