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[209.132.180.67]) by mx.google.com with ESMTP id zw7si334897pac.70.2014.04.09.04.10.02; Wed, 09 Apr 2014 04:10:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932801AbaDILKB (ORCPT + 9 others); Wed, 9 Apr 2014 07:10:01 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:49076 "EHLO mail-pa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932560AbaDILKA (ORCPT ); Wed, 9 Apr 2014 07:10:00 -0400 Received: by mail-pa0-f50.google.com with SMTP id kq14so2368307pab.37 for ; Wed, 09 Apr 2014 04:09:59 -0700 (PDT) X-Received: by 10.68.196.168 with SMTP id in8mr11364929pbc.132.1397041799338; Wed, 09 Apr 2014 04:09:59 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id ci4sm1808351pbb.50.2014.04.09.04.09.56 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 09 Apr 2014 04:09:58 -0700 (PDT) From: Chander Kashyap To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: kgene.kim@samsung.com, Chander Kashyap Subject: [PATCH] arm: exynos: generalize power register address calculation Date: Wed, 9 Apr 2014 16:39:43 +0530 Message-Id: <1397041783-18531-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1396973737-18693-1-git-send-email-chander.kashyap@linaro.org> References: <1396973737-18693-1-git-send-email-chander.kashyap@linaro.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: chander.kashyap@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Currently status/configuration power register values are hard-coded for cpu1. Make it generic so that it is useful for SoC's with more than two cpus. Signed-off-by: Chander Kashyap --- changes in v2 : Used existing macros for clusterid and cpuid calculation arch/arm/mach-exynos/hotplug.c | 15 ++++++++++++--- arch/arm/mach-exynos/platsmp.c | 20 +++++++++++++++----- arch/arm/mach-exynos/regs-pmu.h | 9 +++++++-- 3 files changed, 34 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c index 5eead53..eab6121 100644 --- a/arch/arm/mach-exynos/hotplug.c +++ b/arch/arm/mach-exynos/hotplug.c @@ -17,6 +17,7 @@ #include #include +#include #include #include @@ -92,11 +93,19 @@ static inline void cpu_leave_lowpower(void) static inline void platform_do_lowpower(unsigned int cpu, int *spurious) { + unsigned int mpidr, cpunr, cluster; + + mpidr = cpu_logical_map(cpu); + cpunr = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + /* Maximum possible cpus in a cluster can be 4 */ + cpunr += cluster * 4; for (;;) { - /* make cpu1 to be turned off at next WFI command */ - if (cpu == 1) - __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION); + /* make cpu to be turned off at next WFI command */ + if (cpu) + __raw_writel(0, S5P_ARM_CORE_CONFIGURATION(cpunr)); /* * here's the WFI diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 8ea02f6..8d06b2c 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -92,6 +93,14 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; unsigned long phys_cpu = cpu_logical_map(cpu); + unsigned int mpidr, cpunr, cluster; + + mpidr = cpu_logical_map(cpu); + cpunr = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + /* Maximum possible cpus in a cluster can be 4 */ + cpunr += cluster * 4; /* * Set synchronisation state between this boot processor @@ -109,14 +118,15 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) */ write_pen_release(phys_cpu); - if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) { + if (!(__raw_readl(S5P_ARM_CORE_STATUS(cpunr)) + & S5P_CORE_LOCAL_PWR_EN)) { __raw_writel(S5P_CORE_LOCAL_PWR_EN, - S5P_ARM_CORE1_CONFIGURATION); + S5P_ARM_CORE_CONFIGURATION(cpunr)); timeout = 10; - /* wait max 10 ms until cpu1 is on */ - while ((__raw_readl(S5P_ARM_CORE1_STATUS) + /* wait max 10 ms until secondary cpu is on */ + while ((__raw_readl(S5P_ARM_CORE_STATUS(cpunr)) & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) { if (timeout-- == 0) break; @@ -125,7 +135,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) } if (timeout == 0) { - printk(KERN_ERR "cpu1 power enable failed"); + pr_err("cpu%x power enable failed", cpu); spin_unlock(&boot_lock); return -ETIMEDOUT; } diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 7c029ce..16e17e4 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -104,8 +104,13 @@ #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) -#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) -#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084) +#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) +#define S5P_ARM_CORE0_STATUS S5P_PMUREG(0x2004) + +#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \ + (S5P_ARM_CORE0_CONFIGURATION + 0x80 * _cpunr) +#define S5P_ARM_CORE_STATUS(_cpunr) \ + (S5P_ARM_CORE0_STATUS + 0x80 * _cpunr) #define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) #define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)