From patchwork Mon Aug 12 10:02:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas C Sajjan X-Patchwork-Id: 19007 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qe0-f72.google.com (mail-qe0-f72.google.com [209.85.128.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 65502248EC for ; Mon, 12 Aug 2013 10:02:39 +0000 (UTC) Received: by mail-qe0-f72.google.com with SMTP id a11sf7012418qen.7 for ; Mon, 12 Aug 2013 03:02:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=lDa0WBPFVwllMfaIgTrkfviUG9PTZAratanR0xnKT6w=; b=bN7iAzEiMpJpTHsWlqfFMfFouESng76rwJzQ2cvZz+dhzyek7G12DxH4nw8cVRxqyS Jh0iQOivNnziYDel0MWTKS0T1cdldy1VBqQ80CzY5Ludwz3cUdVHKyInDIsTIqe5kJmg iz2X4IRgzBjgMU7BHmYsppDxlFXfbzt2fQ3vFwB8co6wqs2vsCn7hGG1YPBAekGJKVMD 9K+EW5eA9vclTZIULFxD2YLpgT7NmGcZtTTC3Pici3xxH9I73ySFupnvaY/Rkuh8XGm4 rTbKHCvuT6FYadyPpgfr+D0aYnzg8U6LAOtkwz3NnfzG6JSOIuZY15nVD5bfbnp9DbRg ynYQ== X-Received: by 10.236.163.166 with SMTP id a26mr7624019yhl.22.1376301759222; Mon, 12 Aug 2013 03:02:39 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.29.129 with SMTP id k1ls91910qeh.75.gmail; Mon, 12 Aug 2013 03:02:39 -0700 (PDT) X-Received: by 10.58.164.101 with SMTP id yp5mr6026650veb.0.1376301759126; Mon, 12 Aug 2013 03:02:39 -0700 (PDT) Received: from mail-vb0-f44.google.com (mail-vb0-f44.google.com [209.85.212.44]) by mx.google.com with ESMTPS id r3si8090795vcf.65.2013.08.12.03.02.39 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 12 Aug 2013 03:02:39 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.44 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.44; Received: by mail-vb0-f44.google.com with SMTP id e13so5579613vbg.31 for ; Mon, 12 Aug 2013 03:02:39 -0700 (PDT) X-Gm-Message-State: ALoCoQlohexcub/1kYxhmEacc+seGwr6Vb+gMjee9kDDVLsoM3pICtGuGpIDINaenJN3yjelZIBf X-Received: by 10.220.164.138 with SMTP id e10mr12288676vcy.27.1376301759032; Mon, 12 Aug 2013 03:02:39 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp86953vcz; Mon, 12 Aug 2013 03:02:38 -0700 (PDT) X-Received: by 10.66.161.229 with SMTP id xv5mr12949890pab.87.1376301758216; Mon, 12 Aug 2013 03:02:38 -0700 (PDT) Received: from mail-pa0-f53.google.com (mail-pa0-f53.google.com [209.85.220.53]) by mx.google.com with ESMTPS id gg2si22013540pac.72.2013.08.12.03.02.37 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 12 Aug 2013 03:02:38 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.53 is neither permitted nor denied by best guess record for domain of vikas.sajjan@linaro.org) client-ip=209.85.220.53; Received: by mail-pa0-f53.google.com with SMTP id lb1so7245554pab.40 for ; Mon, 12 Aug 2013 03:02:37 -0700 (PDT) X-Received: by 10.68.178.35 with SMTP id cv3mr3694268pbc.160.1376301757830; Mon, 12 Aug 2013 03:02:37 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id ll5sm38951263pab.19.2013.08.12.03.02.33 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 12 Aug 2013 03:02:36 -0700 (PDT) From: Vikas Sajjan To: mturquette@linaro.org, linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, t.figa@samsung.com, dianders@chromium.org, patches@linaro.org, linaro-kernel@lists.linaro.org Subject: [PATCH 2/2] clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC Date: Mon, 12 Aug 2013 15:32:14 +0530 Message-Id: <1376301734-21847-3-git-send-email-vikas.sajjan@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1376301734-21847-1-git-send-email-vikas.sajjan@linaro.org> References: <1376301734-21847-1-git-send-email-vikas.sajjan@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: vikas.sajjan@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.44 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Adds APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC. Signed-off-by: Vikas Sajjan --- drivers/clk/samsung/clk-exynos5420.c | 81 ++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index e035fd0..42cea7e 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -757,10 +757,81 @@ static struct of_device_id ext_clk_match[] __initdata = { { }, }; +static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(2000000000, 250, 3, 0), + PLL_35XX_RATE(1900000000, 475, 6, 0), + PLL_35XX_RATE(1800000000, 225, 3, 0), + PLL_35XX_RATE(1700000000, 425, 6, 0), + PLL_35XX_RATE(1600000000, 200, 3, 0), + PLL_35XX_RATE(1500000000, 250, 4, 0), + PLL_35XX_RATE(1400000000, 175, 3, 0), + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 200, 2, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(900000000, 150, 2, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(600000000, 200, 2, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(300000000, 400, 4, 3), + PLL_35XX_RATE(200000000, 200, 3, 3), + { }, +}; + +static struct samsung_pll_rate_table kpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 200, 2, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(900000000, 150, 2, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(600000000, 200, 2, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(300000000, 400, 4, 3), + PLL_35XX_RATE(200000000, 200, 3, 3), + { }, +}; + +static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_36XX_RATE(rate, m, p, s, k) */ + PLL_36XX_RATE(192000000, 64, 2, 2, 0), + PLL_36XX_RATE(180633600, 45, 3, 1, 10381), + PLL_36XX_RATE(180000000, 45, 3, 1, 0), + PLL_36XX_RATE(73728000, 98, 2, 4, 19923), + PLL_36XX_RATE(67737600, 90, 2, 4, 20762), + PLL_36XX_RATE(49152000, 98, 3, 4, 19923), + PLL_36XX_RATE(45158400, 90, 3, 4, 20762), + PLL_36XX_RATE(32768000, 131, 3, 5, 4719), + { }, +}; + +static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(533000000, 533, 6, 2), + PLL_35XX_RATE(480000000, 160, 2, 2), + PLL_35XX_RATE(420000000, 140, 2, 2), + PLL_35XX_RATE(350000000, 175, 3, 2), + PLL_35XX_RATE(266000000, 266, 3, 3), + PLL_35XX_RATE(177000000, 118, 2, 3), + PLL_35XX_RATE(100000000, 200, 3, 4), + { }, +}; + /* register exynos5420 clocks */ static void __init exynos5420_clk_init(struct device_node *np) { void __iomem *reg_base; + unsigned long fin_pll_rate; if (np) { reg_base = of_iomap(np, 0); @@ -776,6 +847,16 @@ static void __init exynos5420_clk_init(struct device_node *np) samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), ext_clk_match); + + fin_pll_rate = _get_rate("fin_pll"); + + if (fin_pll_rate == 24 * MHZ) { + exynos5420_plls[apll].rate_table = apll_24mhz_tbl; + exynos5420_plls[kpll].rate_table = kpll_24mhz_tbl; + exynos5420_plls[epll].rate_table = epll_24mhz_tbl; + exynos5420_plls[vpll].rate_table = vpll_24mhz_tbl; + } + samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), reg_base); samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,