From patchwork Fri Jul 5 08:42:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 18267 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qe0-f71.google.com (mail-qe0-f71.google.com [209.85.128.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 331EB25CAB for ; Fri, 5 Jul 2013 08:58:01 +0000 (UTC) Received: by mail-qe0-f71.google.com with SMTP id 1sf2564707qee.10 for ; Fri, 05 Jul 2013 01:58:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=HiKTZ/AzswF05xUs+XBhO7Y9EVkz70/TOKkWGoCRnK8=; b=VGpNwh4nLwWmFmV3C+ktsWIG4Bw3GoGx2ktG7SFxB2eUCpMW5btg20bgnHZeWfQmb1 0uUDjx0CA/5ampRry4gIcwfuIQXQGMRMw2FJX0z0IrKZexGvSqFmRJPUXrKgA3J7Grba ppNhBth55OWCJvmt8GkkRBtl3HtxlKj2oaeNdHN4G/dTwsFj9CTns+dDJ47XFsdRWDOA UmnMEWFmqAk3Gs1UhWZHVBTNTZsCXXLjljSWTXR9/7Hoj1gWdpUkprZz8r6m5p4hEOWH +Bw2BvNz8kVVonbTJJ93B1hLepHk/LEP6va0eZ/FNS934C34CTRoDrwv2msc7y0f8gy6 rssA== X-Received: by 10.236.83.82 with SMTP id p58mr4624824yhe.10.1373014680670; Fri, 05 Jul 2013 01:58:00 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.62.42 with SMTP id v10ls921535qer.27.gmail; Fri, 05 Jul 2013 01:58:00 -0700 (PDT) X-Received: by 10.58.86.70 with SMTP id n6mr6076233vez.8.1373014680390; Fri, 05 Jul 2013 01:58:00 -0700 (PDT) Received: from mail-vc0-f169.google.com (mail-vc0-f169.google.com [209.85.220.169]) by mx.google.com with ESMTPS id o5si2006122vea.4.2013.07.05.01.58.00 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 05 Jul 2013 01:58:00 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.169 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.169; Received: by mail-vc0-f169.google.com with SMTP id ia10so1491155vcb.0 for ; Fri, 05 Jul 2013 01:58:00 -0700 (PDT) X-Received: by 10.220.198.133 with SMTP id eo5mr5977389vcb.24.1373014680245; Fri, 05 Jul 2013 01:58:00 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.149.77 with SMTP id s13csp44549vcv; Fri, 5 Jul 2013 01:57:59 -0700 (PDT) X-Received: by 10.68.98.165 with SMTP id ej5mr8792565pbb.111.1373014679202; Fri, 05 Jul 2013 01:57:59 -0700 (PDT) Received: from mail-pb0-f54.google.com (mail-pb0-f54.google.com [209.85.160.54]) by mx.google.com with ESMTPS id co1si4188566pbc.288.2013.07.05.01.57.58 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 05 Jul 2013 01:57:59 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.160.54 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) client-ip=209.85.160.54; Received: by mail-pb0-f54.google.com with SMTP id ro2so1977459pbb.27 for ; Fri, 05 Jul 2013 01:57:58 -0700 (PDT) X-Received: by 10.66.219.38 with SMTP id pl6mr10611570pac.59.1373014678694; Fri, 05 Jul 2013 01:57:58 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id aj3sm7351050pad.8.2013.07.05.01.57.55 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 05 Jul 2013 01:57:58 -0700 (PDT) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: devicetree-discuss@lists.ozlabs.org, kgene.kim@samsung.com, sachin.kamat@linaro.org, patches@linaro.org, mturquette@linaro.org, inki.dae@samsung.com Subject: [PATCH 1/3] clk: exynos5250: Add G2D gate clock Date: Fri, 5 Jul 2013 14:12:27 +0530 Message-Id: <1373013749-14530-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQl8YwNrZxazf1rY5tfrysFRwx4UUbrhfo0dB68R95J5Gml6B4B1ZOWduKKqmdEqzBhXTePh X-Original-Sender: sachin.kamat@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.169 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Adds gate clock for G2D IP for Exynos5250 SoC. Signed-off-by: Sachin Kamat Cc: Mike Turquette --- This patch depends on the following patch: http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581 --- .../devicetree/bindings/clock/exynos5250-clock.txt | 1 + drivers/clk/samsung/clk-exynos5250.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 1a05761..7e88242 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -155,6 +155,7 @@ clock which they consume. dp 342 mixer 343 hdmi 344 + g2d 345 Example 1: An example of a clock controller node is listed below. diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 6f767c5..3da0bdf 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -62,6 +62,7 @@ #define SRC_CDREX 0x20200 #define PLL_DIV2_SEL 0x20a24 #define GATE_IP_DISP1 0x10928 +#define GATE_IP_ACP 0x10000 /* * Let each supported clock get a unique id. This id is used to lookup the clock @@ -99,7 +100,7 @@ enum exynos5250_clks { spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2, hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct, - wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, + wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, nr_clks, }; @@ -152,6 +153,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = { SRC_CDREX, PLL_DIV2_SEL, GATE_IP_DISP1, + GATE_IP_ACP, }; /* list of all parent clock list */ @@ -463,6 +465,7 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0), GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0), GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0), + GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), }; static __initdata struct of_device_id ext_clk_match[] = {