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[203.254.224.24]) by mx.google.com with ESMTP id o4si11825076pac.105.2013.06.12.08.23.03 for ; Wed, 12 Jun 2013 08:23:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of yadi.brar@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOA009NXDEEMT00@mailout1.samsung.com>; Thu, 13 Jun 2013 00:23:02 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.123]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id F9.2C.29708.65298B15; Thu, 13 Jun 2013 00:23:02 +0900 (KST) X-AuditID: cbfee690-b7f6f6d00000740c-c5-51b892562476 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id A5.05.21068.65298B15; Thu, 13 Jun 2013 00:23:02 +0900 (KST) Received: from localhost.localdomain ([107.108.83.81]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MOA00DGTD5QFP60@mmp2.samsung.com>; Thu, 13 Jun 2013 00:23:02 +0900 (KST) From: Yadwinder Singh Brar To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, dianders@chromium.org, t.figa@samsung.com, vikas.sajjan@linaro.org, patches@linaro.org, Yadwinder Singh Brar Subject: [PATCH v4 6/6] clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC Date: Mon, 03 Jun 2013 20:39:56 +0530 Message-id: <1370272196-4346-7-git-send-email-yadi.brar@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1370272196-4346-1-git-send-email-yadi.brar@samsung.com> References: <1370272196-4346-1-git-send-email-yadi.brar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpmkeLIzCtJLcpLzFFi42JZI2JSrRs2aUegwZnnwhZnlx1ks+hdcJXN YtPja6wWM87vY7J4OuEim8WUw19YLNbPeM1icWzGEkaLJ4+2MVvMmf6OyYHLY3bDRRaPO9f2 sHlsXlLv0bdlFaPH501yAaxRXDYpqTmZZalF+nYJXBm9O9vYCq7LVRyaeYC5gfGgZBcjJ4eE gInEnf2zmCFsMYkL99azdTFycQgJLGWUmLR4HhNMUdesM4wQiemMEleXfmSHcNqYJLa9+MLS xcjBwSZgJPHqmB1Ig4iAqsTntgVgNcwCfxklTr+ezgqSEBYIl7j5cCs7iM0CVHSm/RMbiM0r 4CJx9+wKNohtChKtyw6xg8zkFHCVWD01GsQUAipZv0EZZKSEwCZ2ib07trJCjBGQ+Db5ENgJ EgKyEpsOQD0jKXFwxQ2WCYzCCxgZVjGKphYkFxQnpReZ6BUn5haX5qXrJefnbmIERsDpf88m 7GC8d8D6EGMy0LiJzFKiyfnACMoriTc0NjOyMDUxNTYytzQjTVhJnFe9xTpQSCA9sSQ1OzW1 ILUovqg0J7X4ECMTB6dUA6N2xsLUj8u+7mX8b7zz1QnVQ0ZdWzctE7h7o/9Jxi6zj90CBfbX NL6s9SrYuUkz60uQ7I4P0/0+fw/4fdCyj2v3AaP1qZf2SNtP71r1ed2uD3c8VCImTTJ+v2HS S6NDpe/qj648wrVVRuqhcSRnV7fNETNWF/dJS3yOfQkpfVga/dXPv+SyiXSwEktxRqKhFnNR cSIABD5+SZYCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrAIsWRmVeSWpSXmKPExsVy+t9jQd2wSTsCDfa95LQ4u+wgm0Xvgqts FpseX2O1mHF+H5PF0wkX2SymHP7CYrF+xmsWi2MzljBaPHm0jdlizvR3TA5cHrMbLrJ43Lm2 h81j85J6j74tqxg9Pm+SC2CNamC0yUhNTEktUkjNS85PycxLt1XyDo53jjc1MzDUNbS0MFdS yEvMTbVVcvEJ0HXLzAG6SkmhLDGnFCgUkFhcrKRvh2lCaIibrgVMY4Sub0gQXI+RARpIWMOY 0buzja3gulzFoZkHmBsYD0p2MXJySAiYSHTNOsMIYYtJXLi3nq2LkYtDSGA6o8TVpR/ZIZw2 JoltL76wdDFycLAJGEm8OmYH0iAioCrxuW0BWA2zwF9GidOvp7OCJIQFwiVuPtzKDmKzABWd af/EBmLzCrhI3D27gg1im4JE67JD7CAzOQVcJVZPjQYxhYBK1m9QnsDIu4CRYRWjaGpBckFx UnqukV5xYm5xaV66XnJ+7iZGcHw9k97BuKrB4hCjAAejEg/vhOYdgUKsiWXFlbmHGCU4mJVE eB0mAIV4UxIrq1KL8uOLSnNSiw8xJgPdNJFZSjQ5Hxj7eSXxhsYm5qbGppYmFiZmlqQJK4nz Hmy1DhQSSE8sSc1OTS1ILYLZwsTBKdXAKLyyX+7hVL2v3UsV1hy8vNuDW3pjSlyQxUSlBao9 J8+vrtV/vLB+v+LRyn96d5KOZykX73q532zljZmsd/QSuBdlPhNd1uW/43mC+s/YvoOHm/Ua vgR0KOUqMnjdnWxuo9yXJ/E7ft0hb6bdXBHv5/zy3sDx0tg20r3ilZpuYZFJTbOp2Mc4JZbi jERDLeai4kQAUrtOqPMCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQnk486APIWmTZE94YereLhI/qS+qEiNZc40TzO35t/lKyTUjmT4s1jvQuHjqxtg5G+QhlyW X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::230 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Adds the EPLL and VPLL freq table for exynos5250 SoC. Signed-off-by: Vikas Sajjan --- drivers/clk/samsung/clk-exynos5250.c | 53 ++++++++++++++++++++++++++++++++-- drivers/clk/samsung/clk.h | 2 + 2 files changed, 52 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 70cc6cf..f98c19d 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -472,11 +472,34 @@ static __initdata struct of_device_id ext_clk_match[] = { { }, }; +static __initdata struct samsung_pll_rate_table vpll_24mhz_tbl[] = { + /* sorted in descending order */ + /* PLL_36XX_RATE(rate, m, p, s, k) */ + PLL_36XX_RATE(266000000, 266, 3, 3, 0), + /* Not in UM, but need for eDP on snow */ + PLL_36XX_RATE(70500000, 94, 2, 4, 0), +}; + +static __initdata struct samsung_pll_rate_table epll_24mhz_tbl[] = { + /* sorted in descending order */ + /* PLL_36XX_RATE(rate, m, p, s, k) */ + PLL_36XX_RATE(192000000, 48, 3, 1, 0), + PLL_36XX_RATE(180633600, 45, 3, 1, 10381), + PLL_36XX_RATE(180000000, 45, 3, 1, 0), + PLL_36XX_RATE(73728000, 73, 3, 3, 47710), + PLL_36XX_RATE(67737600, 90, 4, 3, 20762), + PLL_36XX_RATE(49152000, 49, 3, 3, 9962), + PLL_36XX_RATE(45158400, 45, 3, 3, 10381), + PLL_36XX_RATE(32768000, 131, 3, 5, 4719), +}; + /* register exynox5250 clocks */ void __init exynos5250_clk_init(struct device_node *np) { void __iomem *reg_base; struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll; + struct clk *vpllsrc; + unsigned long fin_pll_rate, mout_vpllsrc_rate = 0; if (np) { reg_base = of_iomap(np, 0); @@ -496,6 +519,11 @@ void __init exynos5250_clk_init(struct device_node *np) samsung_clk_register_mux(exynos5250_pll_pmux_clks, ARRAY_SIZE(exynos5250_pll_pmux_clks)); + fin_pll_rate = _get_rate("fin_pll"); + vpllsrc = __clk_lookup("mout_vpllsrc"); + if (vpllsrc) + mout_vpllsrc_rate = clk_get_rate(vpllsrc); + apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", reg_base, NULL, 0); mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", @@ -506,10 +534,29 @@ void __init exynos5250_clk_init(struct device_node *np) reg_base + 0x10050, NULL, 0); cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll", reg_base + 0x10020, NULL, 0); - epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", - reg_base + 0x10030, NULL, 0); - vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc", + + if (fin_pll_rate == (24 * MHZ)) { + epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", + reg_base + 0x10030, epll_24mhz_tbl, + ARRAY_SIZE(epll_24mhz_tbl)); + } else { + pr_warn("%s: valid epll rate_table missing for\n" + "parent fin_pll:%lu hz\n", __func__, fin_pll_rate); + epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", + reg_base + 0x10030, NULL, 0); + } + + if (mout_vpllsrc_rate == (24 * MHZ)) { + vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc" + , reg_base + 0x10040, vpll_24mhz_tbl, + ARRAY_SIZE(vpll_24mhz_tbl)); + } else { + pr_warn("%s: valid vpll rate_table missing for\n" + "parent mout_vpllsrc_rate:%lu hz\n", __func__, + mout_vpllsrc_rate); + samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc", reg_base + 0x10040, NULL, 0); + } samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks, ARRAY_SIZE(exynos5250_fixed_rate_clks)); diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index e4ad6ea..c997649 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -20,6 +20,8 @@ #include #include +#define MHZ (1000*1000) + /** * struct samsung_clock_alias: information about mux clock * @id: platform specific id of the clock.