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[203.254.224.25]) by mx.google.com with ESMTP id ql7si9664539pbc.266.2013.06.12.08.22.18 for ; Wed, 12 Jun 2013 08:22:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of yadi.brar@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOA00I7CDD66TE0@mailout2.samsung.com>; Thu, 13 Jun 2013 00:22:18 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.124]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 7C.37.08825.92298B15; Thu, 13 Jun 2013 00:22:18 +0900 (KST) X-AuditID: cbfee68e-b7f276d000002279-ae-51b8922923ac Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 05.2C.28381.92298B15; Thu, 13 Jun 2013 00:22:17 +0900 (KST) Received: from localhost.localdomain ([107.108.83.81]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MOA00DGTD5QFP60@mmp2.samsung.com>; Thu, 13 Jun 2013 00:22:17 +0900 (KST) From: Yadwinder Singh Brar To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, dianders@chromium.org, t.figa@samsung.com, vikas.sajjan@linaro.org, patches@linaro.org, Yadwinder Singh Brar Subject: [PATCH v4 5/6] clk: samsung: Reorder MUX registration for mout_vpllsrc Date: Mon, 03 Jun 2013 20:39:55 +0530 Message-id: <1370272196-4346-6-git-send-email-yadi.brar@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1370272196-4346-1-git-send-email-yadi.brar@samsung.com> References: <1370272196-4346-1-git-send-email-yadi.brar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpikeLIzCtJLcpLzFFi42JZI2JSo6s1aUegwd057BZnlx1ks+hdcJXN YtPja6wWM87vY7J4OuEim8WUw19YLNbPeM1icWzGEkaLJ4+2MVvMmf6OyYHLY3bDRRaPO9f2 sHlsXlLv0bdlFaPH501yAaxRXDYpqTmZZalF+nYJXBn3Tu5nLngjUHH1/TGWBsbNfF2MnBwS AiYS1ztXMELYYhIX7q1n62Lk4hASWMoo8XLTLWaYovUfTrJDJKYzStx83cAE4bQxSXx4vAyo nYODTcBI4tUxO5AGEQFVic9tC8AamAX+Mkqcfj2dFSQhLOAvsWEhSIKTgwWo6O/B7ywgNq+A i8T2pqlQ2xQkWpcdYgeZySngKrF6ajSIKQRUsn6DMkTFNnaJNc2+EFMEJL5NPsQCUiIhICux 6QDUEEmJgytusExgFF7AyLCKUTS1ILmgOCm9yEivODG3uDQvXS85P3cTIzD8T/971reD8eYB 60OMyUDjJjJLiSbnA+MnryTe0NjMyMLUxNTYyNzSjDRhJXFetRbrQCGB9MSS1OzU1ILUovii 0pzU4kOMTBycUg2MwU+lt5bb/ljBkz2fnUvEJMK6OfBa3u+6spPn5sr+eV3/rWr7t3zLbXFF f65cNlq07dWbW8ttZp8pVFip3WnxepG8/VIp/qCik4E5S75Ihtu5B++9xLqp8uBS4U9RoktD 2lYUBipXz9h2ZbeN2YI3pbvdHvZelT2qN7NxUbfrvE+H7XbtfV3MpcRSnJFoqMVcVJwIAGEN tE2VAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrAIsWRmVeSWpSXmKPExsVy+t9jQV3NSTsCDW7tM7M4u+wgm0Xvgqts FpseX2O1mHF+H5PF0wkX2SymHP7CYrF+xmsWi2MzljBaPHm0jdlizvR3TA5cHrMbLrJ43Lm2 h81j85J6j74tqxg9Pm+SC2CNamC0yUhNTEktUkjNS85PycxLt1XyDo53jjc1MzDUNbS0MFdS yEvMTbVVcvEJ0HXLzAG6SkmhLDGnFCgUkFhcrKRvh2lCaIibrgVMY4Sub0gQXI+RARpIWMOY ce/kfuaCNwIVV98fY2lg3MzXxcjJISFgIrH+w0l2CFtM4sK99WxdjFwcQgLTGSVuvm5ggnDa mCQ+PF7G2MXIwcEmYCTx6pgdSIOIgKrE57YF7CA1zAJ/GSVOv57OCpIQFvCX2LBwAdhUFqCi vwe/s4DYvAIuEtubpjJDbFOQaF12iB1kJqeAq8TqqdEgphBQyfoNyhMYeRcwMqxiFE0tSC4o TkrPNdQrTswtLs1L10vOz93ECI6vZ1I7GFc2WBxiFOBgVOLhfdG6I1CINbGsuDL3EKMEB7OS CK/DBKAQb0piZVVqUX58UWlOavEhxmSgmyYyS4km5wNjP68k3tDYxNzU2NTSxMLEzJI0YSVx 3gOt1oFCAumJJanZqakFqUUwW5g4OKUaGJvmeZUa2TnJqmU8erD46LflT9MqKkNe7X5byPmX g+tRjkLABEaZaduYHq8Pn37v0bqNCiFrVC8cvzfr1IR94qXPfznKHm7PeXLvS036udvHjuXw iK5fz3zv0GXDbafKgj88C43I4VgWvv5Ny7HvBb3H+jY+zqrIdrss576ikbN07e7Y2Mr5sw4q sRRnJBpqMRcVJwIA0mtBVPMCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQn8BkJgyQPXt+1tbzq6CCEALJg7eZTnY0lSjDlwMUW09DtTpYdfAprNSYJidQDaZO7b4bT+ X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::230 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Vikas Sajjan While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the "fout_vpll" (child), we found get rate was failing. So this patch moves the mout_vpllsrc MUX out of the existing common list and registers the mout_vpllsrc MUX before the PLL registrations. Signed-off-by: Vikas Sajjan Signed-off-by: Yadwinder Singh Brar Reviewed-by: Tomasz Figa --- drivers/clk/samsung/clk-exynos5250.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index ddf10ca..70cc6cf 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -207,6 +207,10 @@ struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0), }; +struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { + MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), +}; + struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), @@ -214,7 +218,6 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1), MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), - MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1), MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1), MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1), @@ -490,6 +493,9 @@ void __init exynos5250_clk_init(struct device_node *np) ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), ext_clk_match); + samsung_clk_register_mux(exynos5250_pll_pmux_clks, + ARRAY_SIZE(exynos5250_pll_pmux_clks)); + apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", reg_base, NULL, 0); mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",