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Thu, 13 Jun 2013 00:21:32 +0900 (KST) From: Yadwinder Singh Brar To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, dianders@chromium.org, t.figa@samsung.com, vikas.sajjan@linaro.org, patches@linaro.org Subject: [PATCH v4 4/6] clk: samsung: Add set_rate() clk_ops for PLL36xx Date: Mon, 03 Jun 2013 20:39:54 +0530 Message-id: <1370272196-4346-5-git-send-email-yadi.brar@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1370272196-4346-1-git-send-email-yadi.brar@samsung.com> References: <1370272196-4346-1-git-send-email-yadi.brar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRmVeSWpSXmKPExsWyRsSkTvfPxB2BBnu+S1icXXaQzaJ3wVU2 i02Pr7FazDi/j8ni6YSLbBZTDn9hsVg/4zWLxbEZSxgtnjzaxuzA6TG74SKLx51re9g8Ni+p 9+jbsorR4/MmuQDWKC6blNSczLLUIn27BK6MnTedC5pUKt79NW5gnCrXxcjJISFgIjFv9jtm CFtM4sK99WwgtpDAUkaJ7qnScDUvzwPVcAHFpzNK/Dh1EMppY5I4t3U5kMPBwSZgJPHqmB1I g4iAqsTntgXsIDXMAmcZJfbevcgOUiMs4CHRfUENpIYFqGbF4RUsIDavgIvEo2uboY5QkGhd dgisnFPAVWL11GgQUwioZP0GZZCJEgLL2CW2nzjKBjFGQOLb5EMsIDUSArISmw5ATZGUOLji BssERuEFjAyrGEVTC5ILipPSi0z0ihNzi0vz0vWS83M3MQLD/fS/ZxN2MN47YH2IMRlo3ERm KdHkfGC85JXEGxqbGVmYmpgaG5lbmpEmrCTOq95iHSgkkJ5YkpqdmlqQWhRfVJqTWnyIkYmD U6qBcYqsLYuokqmgteJ110muX+6Upd3Zefq7+rvzizjqpVy+e288bdi5sejMgpaf064GfD5y Vf7C1+bNL8xupsdp6609aeLx5fH03WvWhpbOvHipQcnicWLzXyOm5GUv+la49N1hVNvrtvlQ iM+cGwwGHFwfyhnu65/m6b6pGsI6wyHjxN8lQiYuMkosxRmJhlrMRcWJAC30Wz2NAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBIsWRmVeSWpSXmKPExsVy+t9jQd0/E3cEGqzp47M4u+wgm0Xvgqts FpseX2O1mHF+H5PF0wkX2SymHP7CYrF+xmsWi2MzljBaPHm0jdmB02N2w0UWjzvX9rB5bF5S 79G3ZRWjx+dNcgGsUQ2MNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2 Si4+AbpumTlABykplCXmlAKFAhKLi5X07TBNCA1x07WAaYzQ9Q0JgusxMkADCWsYM3bedC5o Uql499e4gXGqXBcjJ4eEgInEvJfnmSFsMYkL99azdTFycQgJTGeU+HHqIDOE08YkcW7rciCH g4NNwEji1TE7kAYRAVWJz20L2EFqmAXOMkrsvXuRHaRGWMBDovuCGkgNC1DNisMrWEBsXgEX iUfXNkMtU5BoXXYIrJxTwFVi9dRoEFMIqGT9BuUJjLwLGBlWMYqmFiQXFCel5xrpFSfmFpfm pesl5+duYgTH0zPpHYyrGiwOMQpwMCrx8E5o3hEoxJpYVlyZe4hRgoNZSYTXYQJQiDclsbIq tSg/vqg0J7X4EGMy0E0TmaVEk/OBsZ5XEm9obGJuamxqaWJhYmZJmrCSOO/BVutAIYH0xJLU 7NTUgtQimC1MHJxSDYw1yjtav3044xrt7tifJvSiecObj3UGKzj3iyk+827Wsr31udXk37pp jX/uH/pz1vN6et2L9KA1D/ef1j2Ssm5XjtWui5FcgkazPmbYeZx4dUHvrKaW/Hv/4LSlGy2m 8Xj/YbsztWXtHJW7BSvi+ls2KucuVRKsWM/7abaKgPW05/Ez/J6qOpxRYinOSDTUYi4qTgQA FrSXeOsCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQlqn1DtSID2oS1wt1yw8mAHJ+dS213Qfg15j/iBwvFtjqHxYZm/zGi5NGQSkr45v36/KmiY X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::234 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Vikas Sajjan This patch adds set_rate and round_rate clk_ops for PLL36xx Reviewed-by: Tomasz Figa Reviewed-by: Doug Anderson Signed-off-by: Vikas Sajjan Reviewed-by: Tomasz Figa --- drivers/clk/samsung/clk-pll.c | 79 ++++++++++++++++++++++++++++++++++++++++- 1 files changed, 78 insertions(+), 1 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 319b52b..42b60b5 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -215,6 +215,9 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name, #define PLL36XX_CON0_OFFSET (0x100) #define PLL36XX_CON1_OFFSET (0x104) +/* Maximum lock time can be 3000 * PDIV cycles */ +#define PLL36XX_LOCK_FACTOR (3000) + #define PLL36XX_KDIV_MASK (0xFFFF) #define PLL36XX_MDIV_MASK (0x1FF) #define PLL36XX_PDIV_MASK (0x3F) @@ -222,6 +225,8 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name, #define PLL36XX_MDIV_SHIFT (16) #define PLL36XX_PDIV_SHIFT (8) #define PLL36XX_SDIV_SHIFT (0) +#define PLL36XX_KDIV_SHIFT (0) +#define PLL36XX_LOCK_STAT_SHIFT (29) static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -244,8 +249,78 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, return (unsigned long)fvco; } +static inline bool samsung_pll36xx_mpk_change( + const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1) +{ + u32 old_mdiv, old_pdiv, old_kdiv; + + old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; + old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; + old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK; + + return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || + rate->kdiv != old_kdiv); +} + +static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp, pll_con0, pll_con1; + const struct samsung_pll_rate_table *rate; + + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET); + pll_con1 = pll_readl(pll, PLL36XX_CON1_OFFSET); + + if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) { + /* If only s change, change just s value only*/ + pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT); + pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); + pll_writel(pll, pll_con0, PLL36XX_CON0_OFFSET); + return 0; + } + + /* Set PLL lock time. */ + pll_writel(pll, (rate->pdiv * PLL36XX_LOCK_FACTOR), + PLL36XX_LOCK_OFFSET); + + /* Change PLL PMS values */ + pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) | + (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) | + (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT)); + pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | + (rate->pdiv << PLL36XX_PDIV_SHIFT) | + (rate->sdiv << PLL36XX_SDIV_SHIFT); + pll_writel(pll, pll_con0, PLL36XX_CON0_OFFSET); + + pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT); + pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; + pll_writel(pll, pll_con1, PLL36XX_CON1_OFFSET); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = pll_readl(pll, PLL36XX_CON0_OFFSET); + } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT))); + + return 0; +} + static const struct clk_ops samsung_pll36xx_clk_ops = { .recalc_rate = samsung_pll36xx_recalc_rate, + .set_rate = samsung_pll36xx_set_rate, + .round_rate = samsung_pll_round_rate, +}; + +static const struct clk_ops samsung_pll36xx_clk_min_ops = { + .recalc_rate = samsung_pll36xx_recalc_rate, }; struct clk * __init samsung_clk_register_pll36xx(const char *name, @@ -264,7 +339,6 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name, } init.name = name; - init.ops = &samsung_pll36xx_clk_ops; init.flags = CLK_GET_RATE_NOCACHE; init.parent_names = &pname; init.num_parents = 1; @@ -273,6 +347,9 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name, pll->rate_count = rate_count; pll->rate_table = kmemdup(rate_table, rate_count * sizeof(struct samsung_pll_rate_table), GFP_KERNEL); + init.ops = &samsung_pll36xx_clk_ops; + } else { + init.ops = &samsung_pll36xx_clk_min_ops; } pll->hw.init = &init;