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Thu, 13 Jun 2013 00:20:50 +0900 (KST) From: Yadwinder Singh Brar To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, dianders@chromium.org, t.figa@samsung.com, vikas.sajjan@linaro.org, patches@linaro.org, Yadwinder Singh Brar Subject: [PATCH v4 3/6] clk: samsung: Add set_rate() clk_ops for PLL35xx Date: Mon, 03 Jun 2013 20:39:53 +0530 Message-id: <1370272196-4346-4-git-send-email-yadi.brar@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1370272196-4346-1-git-send-email-yadi.brar@samsung.com> References: <1370272196-4346-1-git-send-email-yadi.brar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpikeLIzCtJLcpLzFFi42JZI2JSo3tp4o5Ag9PbrS3OLjvIZtG74Cqb xabH11gtZpzfx2TxdMJFNosph7+wWKyf8ZrF4tiMJYwWTx5tY7aYM/0dkwOXx+yGiywed67t YfPYvKTeo2/LKkaPz5vkAlijuGxSUnMyy1KL9O0SuDL+zv/OWNCoUfFx8Q3GBsZzCl2MnBwS AiYSk3b0MkLYYhIX7q1n62Lk4hASWMoo0fN7AhNM0dWuM1CJ6YwScy5sYIdw2pgk1i47C1TF wcEmYCTx6pgdSIOIgKrE57YFYDXMAn8ZJU6/ns4KkhAW8JD4/fgaM0g9C1DR2VkyIGFeAReJ 161fmSGWKUi0LjvEDlLCKeAqsXpqNIgpBFSyfoMyyEQJgXXsEqf7j7CDlLMICEh8m3yIBaRG QkBWYtMBqCmSEgdX3GCZwCi8gJFhFaNoakFyQXFSepGRXnFibnFpXrpecn7uJkZg+J/+96xv B+PNA9aHGJOBxk1klhJNzgfGT15JvKGxmZGFqYmpsZG5pRlpwkrivGot1oFCAumJJanZqakF qUXxRaU5qcWHGJk4OKUaGJUWsUrtW/naxW/+3Qs1Zwomt0Uu6q9P//jy7S/JuO9Vj51y49le FJppP9ScEvfHZtJKm5++clwtokvOV5xZm6rzwmP/3b+vGfTu3a5Kiun3vSW1+ayOfcNB2WMz ONhWryorFS0/o3ZOt/VkepLEZ99XcTsiWVo4Qj8Y5nnZe37RfK9S6J4wQYmlOCPRUIu5qDgR AEbQnG6VAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPIsWRmVeSWpSXmKPExsVy+t9jQd1LE3cEGiz4amBxdtlBNoveBVfZ LDY9vsZqMeP8PiaLpxMusllMOfyFxWL9jNcsFsdmLGG0ePJoG7PFnOnvmBy4PGY3XGTxuHNt D5vH5iX1Hn1bVjF6fN4kF8Aa1cBok5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6k kJeYm2qr5OIToOuWmQN0lZJCWWJOKVAoILG4WEnfDtOE0BA3XQuYxghd35AguB4jAzSQsIYx 4+/874wFjRoVHxffYGxgPKfQxcjJISFgInG16wwbhC0mceHeeiCbi0NIYDqjxJwLG9ghnDYm ibXLzjJ1MXJwsAkYSbw6ZgfSICKgKvG5bQFYDbPAX0aJ06+ns4IkhAU8JH4/vsYMUs8CVHR2 lgxImFfAReJ161dmiGUKEq3LDrGDlHAKuEqsnhoNYgoBlazfoDyBkXcBI8MqRtHUguSC4qT0 XEO94sTc4tK8dL3k/NxNjODoeia1g3Flg8UhRgEORiUe3hetOwKFWBPLiitzDzFKcDArifA6 TAAK8aYkVlalFuXHF5XmpBYfYkwGOmkis5Rocj4w8vNK4g2NTcxNjU0tTSxMzCxJE1YS5z3Q ah0oJJCeWJKanZpakFoEs4WJg1OqgVEt3m/ru8TUTpXbLMUzI3Wn31xp4yHc0iD6WFdX85bH 8Uk6PSI2peyP2x/43T/FuObcW2bpfdetE4Sqy96EWbaF3w1Y/rFt2cW/KZnfuR88OsOyQdT2 XtME/5qXnSXrOibMFVDNC/KVqglUXr/41wEZ2S9e802kb5RF+HC1ahzRfrTjqNK0XiWW4oxE Qy3mouJEAKwI1yHyAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQnsLsqNSJr3+nIhaZM5v/ylwEsfpCeA5IoUBZC6NwB4IQ1qvRjYbeYQUCSOQIx7USHQyBKn X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::234 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch add set_rate() and round_rate() for PLL35xx Reviewed-by: Doug Anderson Signed-off-by: Yadwinder Singh Brar Reviewed-by: Tomasz Figa --- drivers/clk/samsung/clk-pll.c | 104 ++++++++++++++++++++++++++++++++++++++++- 1 files changed, 103 insertions(+), 1 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index cba73a4..319b52b 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -27,6 +27,37 @@ struct samsung_clk_pll { #define pll_writel(pll, val, offset) \ __raw_writel(val, (void __iomem *)(pll->base + (offset))); +static const struct samsung_pll_rate_table *samsung_get_pll_settings( + struct samsung_clk_pll *pll, unsigned long rate) +{ + const struct samsung_pll_rate_table *rate_table = pll->rate_table; + int i; + + for (i = 0; i < pll->rate_count; i++) { + if (rate == rate_table[i].rate) + return &rate_table[i]; + } + + return NULL; +} + +static long samsung_pll_round_rate(struct clk_hw *hw, + unsigned long drate, unsigned long *prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate_table = pll->rate_table; + int i; + + /* Assumming rate_table is in descending order */ + for (i = 0; i < pll->rate_count; i++) { + if (drate >= rate_table[i].rate) + return rate_table[i].rate; + } + + /* return minimum supported value */ + return rate_table[i - 1].rate; +} + /* * PLL35xx Clock Type */ @@ -34,12 +65,17 @@ struct samsung_clk_pll { #define PLL35XX_CON0_OFFSET (0x100) #define PLL35XX_CON1_OFFSET (0x104) +/* Maximum lock time can be 270 * PDIV cycles */ +#define PLL35XX_LOCK_FACTOR (270) + #define PLL35XX_MDIV_MASK (0x3FF) #define PLL35XX_PDIV_MASK (0x3F) #define PLL35XX_SDIV_MASK (0x7) +#define PLL35XX_LOCK_STAT_MASK (0x1) #define PLL35XX_MDIV_SHIFT (16) #define PLL35XX_PDIV_SHIFT (8) #define PLL35XX_SDIV_SHIFT (0) +#define PLL35XX_LOCK_STAT_SHIFT (29) static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -59,8 +95,72 @@ static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, return (unsigned long)fvco; } +static inline bool samsung_pll35xx_mp_change( + const struct samsung_pll_rate_table *rate, u32 pll_con) +{ + u32 old_mdiv, old_pdiv; + + old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; + old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; + + return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); +} + +static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 tmp; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + tmp = pll_readl(pll, PLL35XX_CON0_OFFSET); + + if (!(samsung_pll35xx_mp_change(rate, tmp))) { + /* If only s change, change just s value only*/ + tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT); + tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; + pll_writel(pll, tmp, PLL35XX_CON0_OFFSET); + } else { + /* Set PLL lock time. */ + pll_writel(pll, rate->pdiv * PLL35XX_LOCK_FACTOR, + PLL35XX_LOCK_OFFSET); + + /* Change PLL PMS values */ + tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) | + (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) | + (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT)); + tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | + (rate->pdiv << PLL35XX_PDIV_SHIFT) | + (rate->sdiv << PLL35XX_SDIV_SHIFT); + pll_writel(pll, tmp, PLL35XX_CON0_OFFSET); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = pll_readl(pll, PLL35XX_CON0_OFFSET); + } while (!(tmp & (PLL35XX_LOCK_STAT_MASK + << PLL35XX_LOCK_STAT_SHIFT))); + } + + return 0; +} + static const struct clk_ops samsung_pll35xx_clk_ops = { .recalc_rate = samsung_pll35xx_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll35xx_set_rate, +}; + +static const struct clk_ops samsung_pll35xx_clk_min_ops = { + .recalc_rate = samsung_pll35xx_recalc_rate, }; struct clk * __init samsung_clk_register_pll35xx(const char *name, @@ -79,7 +179,6 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name, } init.name = name; - init.ops = &samsung_pll35xx_clk_ops; init.flags = CLK_GET_RATE_NOCACHE; init.parent_names = &pname; init.num_parents = 1; @@ -88,6 +187,9 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name, pll->rate_count = rate_count; pll->rate_table = kmemdup(rate_table, rate_count * sizeof(struct samsung_pll_rate_table), GFP_KERNEL); + init.ops = &samsung_pll35xx_clk_ops; + } else { + init.ops = &samsung_pll35xx_clk_min_ops; } pll->hw.init = &init;