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[203.254.224.33]) by mx.google.com with ESMTP id ra8si11802175pab.207.2013.06.12.08.20.05 for ; Wed, 12 Jun 2013 08:20:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of yadi.brar@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOA00H8ID9GQO40@mailout3.samsung.com>; Thu, 13 Jun 2013 00:20:04 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.124]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 63.FB.29708.4A198B15; Thu, 13 Jun 2013 00:20:04 +0900 (KST) X-AuditID: cbfee690-b7f6f6d00000740c-05-51b891a4e754 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 03.C4.21068.4A198B15; Thu, 13 Jun 2013 00:20:04 +0900 (KST) Received: from localhost.localdomain ([107.108.83.81]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MOA00DGTD5QFP60@mmp2.samsung.com>; Thu, 13 Jun 2013 00:20:04 +0900 (KST) From: Yadwinder Singh Brar To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, dianders@chromium.org, t.figa@samsung.com, vikas.sajjan@linaro.org, patches@linaro.org, Yadwinder Singh Brar Subject: [PATCH v4 2/6] clk: samsung: Add support to register rate_table for PLL3xxx Date: Mon, 03 Jun 2013 20:39:52 +0530 Message-id: <1370272196-4346-3-git-send-email-yadi.brar@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1370272196-4346-1-git-send-email-yadi.brar@samsung.com> References: <1370272196-4346-1-git-send-email-yadi.brar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpikeLIzCtJLcpLzFFi42JZI2JSo7tk4o5Ag40vhS3OLjvIZtG74Cqb xabH11gtZpzfx2TxdMJFNosph7+wWKyf8ZrF4tiMJYwWTx5tY7aYM/0dkwOXx+yGiywed67t YfPYvKTeo2/LKkaPz5vkAlijuGxSUnMyy1KL9O0SuDIuNLQxF9w0qmh5/Z+5gbFTs4uRg0NC wERiRothFyMnkCkmceHeerYuRi4OIYGljBL3W1YxQyRMJHrXTGWFSExnlPjY1MoI4bQxSTw6 sIkJZBKbgJHEq2N2IA0iAqoSn9sWsIPUMAv8ZZQ4/Xo6K0hCWCBMYvXPaYwgNgtQ0Y7JS8Fs XgEXiYeN+9ghtilItC47xA4yk1PAVWL11GgQUwioZP0GZZCREgKb2CUWftnABDFGQOLb5EMs EM/ISmw6AHWzpMTBFTdYJjAKL2BkWMUomlqQXFCclF5kolecmFtcmpeul5yfu4kRGP6n/z2b sIPx3gHrQ4zJQOMmMkuJJucD4yevJN7Q2MzIwtTE1NjI3NKMNGElcV71FutAIYH0xJLU7NTU gtSi+KLSnNTiQ4xMHJxSDYyWh4RvKmnc98l4dOCr88wg/tNP1njPFXAIEOLz9K3cE8jcdF21 23z1xFtPZqisF/s3qc3O83P5PpXCa9w/NA7sqp4heK784I4fm6RCLCZNOuwd8evcyYsXHxee Dk7e8KTs8AuXv/1z9bd6MFjc2DRrcZFc9tNV1nt11pUbCARoT9cJ3XRl+8TzSizFGYmGWsxF xYkAjrpsU5UCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrAIsWRmVeSWpSXmKPExsVy+t9jQd0lE3cEGiyYw2lxdtlBNoveBVfZ LDY9vsZqMeP8PiaLpxMusllMOfyFxWL9jNcsFsdmLGG0ePJoG7PFnOnvmBy4PGY3XGTxuHNt D5vH5iX1Hn1bVjF6fN4kF8Aa1cBok5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6k kJeYm2qr5OIToOuWmQN0lZJCWWJOKVAoILG4WEnfDtOE0BA3XQuYxghd35AguB4jAzSQsIYx 40JDG3PBTaOKltf/mRsYOzW7GDk5JARMJHrXTGWFsMUkLtxbz9bFyMUhJDCdUeJjUysjhNPG JPHowCamLkYODjYBI4lXx+xAGkQEVCU+ty1gB6lhFvjLKHH69XSwScICYRKrf05jBLFZgIp2 TF4KZvMKuEg8bNzHDrFNQaJ12SF2kJmcAq4Sq6dGg5hCQCXrNyhPYORdwMiwilE0tSC5oDgp PddIrzgxt7g0L10vOT93EyM4vp5J72Bc1WBxiFGAg1GJh3dC845AIdbEsuLK3EOMEhzMSiK8 DhOAQrwpiZVVqUX58UWlOanFhxiTgW6ayCwlmpwPjP28knhDYxNzU2NTSxMLEzNL0oSVxHkP tloHCgmkJ5akZqemFqQWwWxh4uCUamAM3d81O3W+mM3EhJe7pUUrZCdIbap4U+9z90ty+hFW 9vUSZ8VbNE077m3YPWmZQGrjnNuR8o2scqunRrzwuTRF6N7mPcd2vTlnzOxbwKmY8HNO0Y/9 vqwrF79KMv/fGq2x6abt/N5ZhxWcr225FHPsksOdh1Hr1YucmI9cXl7z9M5dTc9665vrlFiK MxINtZiLihMBRkboWPMCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQno/9aLqIvvYQ1unnBVrNguP3LreUEZdHBDH3tNv7Xaxb/Gg/Gw3ycdUYURI7dN3rLtMnbE X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.169 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch defines a common rate_table which will contain recommended p, m, s, k values for supported rates that needs to be changed for changing corresponding PLL's rate. Reviewed-by: Doug Anderson Signed-off-by: Yadwinder Singh Brar --- drivers/clk/samsung/clk-exynos4.c | 8 +++--- drivers/clk/samsung/clk-exynos5250.c | 14 ++++++------ drivers/clk/samsung/clk-pll.c | 22 +++++++++++++++++++- drivers/clk/samsung/clk-pll.h | 35 ++++++++++++++++++++++++++++++++- 4 files changed, 64 insertions(+), 15 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index ba33bc6..e02a342 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1028,13 +1028,13 @@ void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_so reg_base + VPLL_CON0, pll_4650c); } else { apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", - reg_base + APLL_LOCK); + reg_base + APLL_LOCK, NULL, 0); mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", - reg_base + E4X12_MPLL_LOCK); + reg_base + E4X12_MPLL_LOCK, NULL, 0); epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", - reg_base + EPLL_LOCK); + reg_base + EPLL_LOCK, NULL, 0); vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll", - reg_base + VPLL_LOCK); + reg_base + VPLL_LOCK, NULL, 0); } samsung_clk_add_lookup(apll, fout_apll); diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 687b580..ddf10ca 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np) ext_clk_match); apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", - reg_base); + reg_base, NULL, 0); mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", - reg_base + 0x4000); + reg_base + 0x4000, NULL, 0); bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll", - reg_base + 0x20010); + reg_base + 0x20010, NULL, 0); gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll", - reg_base + 0x10050); + reg_base + 0x10050, NULL, 0); cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll", - reg_base + 0x10020); + reg_base + 0x10020, NULL, 0); epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", - reg_base + 0x10030); + reg_base + 0x10030, NULL, 0); vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc", - reg_base + 0x10040); + reg_base + 0x10040, NULL, 0); samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks, ARRAY_SIZE(exynos5250_fixed_rate_clks)); diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index a7d8ad9..cba73a4 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -16,6 +16,8 @@ struct samsung_clk_pll { struct clk_hw hw; const void __iomem *base; + const struct samsung_pll_rate_table *rate_table; + unsigned int rate_count; }; #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw) @@ -62,7 +64,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops = { }; struct clk * __init samsung_clk_register_pll35xx(const char *name, - const char *pname, const void __iomem *base) + const char *pname, const void __iomem *base, + const struct samsung_pll_rate_table *rate_table, + const unsigned int rate_count) { struct samsung_clk_pll *pll; struct clk *clk; @@ -80,6 +84,12 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name, init.parent_names = &pname; init.num_parents = 1; + if (rate_table && rate_count) { + pll->rate_count = rate_count; + pll->rate_table = kmemdup(rate_table, rate_count * + sizeof(struct samsung_pll_rate_table), GFP_KERNEL); + } + pll->hw.init = &init; pll->base = base; @@ -137,7 +147,9 @@ static const struct clk_ops samsung_pll36xx_clk_ops = { }; struct clk * __init samsung_clk_register_pll36xx(const char *name, - const char *pname, const void __iomem *base) + const char *pname, const void __iomem *base, + const struct samsung_pll_rate_table *rate_table, + const unsigned int rate_count) { struct samsung_clk_pll *pll; struct clk *clk; @@ -155,6 +167,12 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name, init.parent_names = &pname; init.num_parents = 1; + if (rate_table && rate_count) { + pll->rate_count = rate_count; + pll->rate_table = kmemdup(rate_table, rate_count * + sizeof(struct samsung_pll_rate_table), GFP_KERNEL); + } + pll->hw.init = &init; pll->base = base; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 1329522..4780e6c 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -12,6 +12,33 @@ #ifndef __SAMSUNG_CLK_PLL_H #define __SAMSUNG_CLK_PLL_H +#define PLL_35XX_RATE(_rate, _m, _p, _s) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + } + +#define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \ + { \ + .rate = (_rate), \ + .mdiv = (_m), \ + .pdiv = (_p), \ + .sdiv = (_s), \ + .kdiv = (_k), \ + } + +/* NOTE: Rate table should be kept sorted in descending order. */ + +struct samsung_pll_rate_table { + unsigned int rate; + unsigned int pdiv; + unsigned int mdiv; + unsigned int sdiv; + unsigned int kdiv; +}; + enum pll45xx_type { pll_4500, pll_4502, @@ -25,9 +52,13 @@ enum pll46xx_type { }; extern struct clk * __init samsung_clk_register_pll35xx(const char *name, - const char *pname, const void __iomem *base); + const char *pname, const void __iomem *base, + const struct samsung_pll_rate_table *rate_table, + const unsigned int rate_count); extern struct clk * __init samsung_clk_register_pll36xx(const char *name, - const char *pname, const void __iomem *base); + const char *pname, const void __iomem *base, + const struct samsung_pll_rate_table *rate_table, + const unsigned int rate_count); extern struct clk * __init samsung_clk_register_pll45xx(const char *name, const char *pname, const void __iomem *con_reg, enum pll45xx_type type);