From patchwork Wed Feb 27 10:36:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inderpal Singh X-Patchwork-Id: 15118 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id CC1BD23E0D for ; Wed, 27 Feb 2013 10:36:25 +0000 (UTC) Received: from mail-ve0-f173.google.com (mail-ve0-f173.google.com [209.85.128.173]) by fiordland.canonical.com (Postfix) with ESMTP id 79C51A18C95 for ; Wed, 27 Feb 2013 10:36:25 +0000 (UTC) Received: by mail-ve0-f173.google.com with SMTP id oz10so378695veb.18 for ; Wed, 27 Feb 2013 02:36:25 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=YTD8vSngRhUBsK3/jxpoJkYQND2MfMkX7Wezs8cfRtQ=; b=TV2BeE0U8i2lG6nnWxew/ofC0xMUccL0HNR8nmjYB3TEoSNKFu/bSG1LCzjq3sbWPR 7Lp7D/HHjOilzNnygsc9MVuT8EYkhPKD1CP+g1Bsj0P0fvgtwC1nRX086TUTYMwOp/WT Pbu8+YTLPOH63fW0u/VX5+D7GAkJ1EPLyfc/jGo1hZXBQwsYFhTGQ6dFFrTdlpE621Cn wMhFfq4rdDEoJtV/1z2zB08scMsgk4IoC/FAXdgvcVGjUCmPcG4TfgftLd47Uj2MH73E 8JuCCci9iKqeFqg5DqPj0kPudZVBRfUigGxS1K+T+OpQLqnnyMBeYlrTrkazSE9u3xC7 +RQw== X-Received: by 10.58.188.48 with SMTP id fx16mr699389vec.22.1361961384959; Wed, 27 Feb 2013 02:36:24 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.145.101 with SMTP id st5csp159463veb; Wed, 27 Feb 2013 02:36:24 -0800 (PST) X-Received: by 10.68.48.227 with SMTP id p3mr2695126pbn.34.1361961383359; Wed, 27 Feb 2013 02:36:23 -0800 (PST) Received: from mail-pb0-f54.google.com (mail-pb0-f54.google.com [209.85.160.54]) by mx.google.com with ESMTPS id jy6si4159311pbc.149.2013.02.27.02.36.22 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 27 Feb 2013 02:36:23 -0800 (PST) Received-SPF: neutral (google.com: 209.85.160.54 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) client-ip=209.85.160.54; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.54 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) smtp.mail=inderpal.singh@linaro.org Received: by mail-pb0-f54.google.com with SMTP id rr4so294092pbb.13 for ; Wed, 27 Feb 2013 02:36:22 -0800 (PST) X-Received: by 10.66.250.169 with SMTP id zd9mr6830641pac.134.1361961382498; Wed, 27 Feb 2013 02:36:22 -0800 (PST) Received: from inder-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPS id w2sm4917406pax.22.2013.02.27.02.36.19 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 27 Feb 2013 02:36:21 -0800 (PST) From: Inderpal Singh To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: linux@arm.linux.org.uk, kgene.kim@samsung.com, patches@linaro.org Subject: [PATCH v3] arm: plat-samsung: check processor type before cache restoration in resume Date: Wed, 27 Feb 2013 16:06:03 +0530 Message-Id: <1361961363-28412-1-git-send-email-inderpal.singh@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQkcfrhThYa9SNz7KfKgFBBX9xoRmQUYFr7mMdXMHSm2jzgDfwVhyoYU6aPUt4SaXNbm9t3G Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence check the same before restoring the cache in resume. This is needed for single kernel image. Signed-off-by: Inderpal Singh --- changes in v2: - check processor midr instead of checking all soc ids as suggested by Kukjin changes in v3: - simplify by reading midr in assembly as per Russell arch/arm/plat-samsung/s5p-sleep.S | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index bdf6dad..6e15993 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S @@ -25,6 +25,9 @@ #include #include +#define CPU_MASK 0xff0ffff0 +#define CPU_CORTEX_A9 0x410fc090 + /* * The following code is located into the .data section. This is to * allow l2x0_regs_phys to be accessed with a relative load while we @@ -51,6 +54,12 @@ ENTRY(s3c_cpu_resume) #ifdef CONFIG_CACHE_L2X0 + mrc p15, 0, r0, c0, c0, 0 + ldr r1, =CPU_MASK + and r0, r0, r1 + ldr r1, =CPU_CORTEX_A9 + cmp r0, r1 + bne resume_l2on adr r0, l2x0_regs_phys ldr r0, [r0] ldr r1, [r0, #L2X0_R_PHY_BASE]