From patchwork Tue Feb 26 09:56:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inderpal Singh X-Patchwork-Id: 15086 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 122CD23E1F for ; Tue, 26 Feb 2013 09:57:08 +0000 (UTC) Received: from mail-ve0-f173.google.com (mail-ve0-f173.google.com [209.85.128.173]) by fiordland.canonical.com (Postfix) with ESMTP id A1AA7A190F6 for ; Tue, 26 Feb 2013 09:57:07 +0000 (UTC) Received: by mail-ve0-f173.google.com with SMTP id oz10so3164847veb.4 for ; Tue, 26 Feb 2013 01:57:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=fPegCYSojvrbK8iMzYTbkuDrPDtpxr5UkFYj34G+wP0=; b=mrpaZlwyDy/b7sFLJ/BXzGqNJNOR11pl/cR6PPse/jvGX72Vyiqegv5sv15m2CdL8Z z5EiMMERgxREvXR+Z6gPztg/7Z/SUhBVyE4A9+gdiBOqPqIY2UtUBlo7OO9HzvmIDITy 1+3bEFBhb4j4S2Jkm/Ult+52v1dWIsFFCWsiadP4Cc6ab4WjcZ17GISCigciIXg4Ds5Z SpWit2+yySieHLuwR3HacBtBmlXIPNiBrliyD6pbS2JL+82MxCXp07+7SlmoKDQtoRZL 3V0tMtc8/N7kIsj4m5XwJWTi/WayvAWr+uzCKP7Yb7AuNx3CDSEpZLOoQe6sY8tP2hyV lIVQ== X-Received: by 10.52.29.18 with SMTP id f18mr9838299vdh.57.1361872627079; Tue, 26 Feb 2013 01:57:07 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.145.101 with SMTP id st5csp105277veb; Tue, 26 Feb 2013 01:57:06 -0800 (PST) X-Received: by 10.66.218.100 with SMTP id pf4mr897570pac.94.1361872625919; Tue, 26 Feb 2013 01:57:05 -0800 (PST) Received: from mail-pa0-f50.google.com (mail-pa0-f50.google.com [209.85.220.50]) by mx.google.com with ESMTPS id t10si685570pay.273.2013.02.26.01.57.05 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 26 Feb 2013 01:57:05 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.50 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) client-ip=209.85.220.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.50 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) smtp.mail=inderpal.singh@linaro.org Received: by mail-pa0-f50.google.com with SMTP id fa11so2336392pad.9 for ; Tue, 26 Feb 2013 01:57:05 -0800 (PST) X-Received: by 10.68.224.169 with SMTP id rd9mr22411957pbc.199.1361872625177; Tue, 26 Feb 2013 01:57:05 -0800 (PST) Received: from inder-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPS id i6sm909833paw.19.2013.02.26.01.57.01 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 26 Feb 2013 01:57:04 -0800 (PST) From: Inderpal Singh To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: kgene.kim@samsung.com, patches@linaro.org Subject: [PATCH v2] arm: plat-samsung: check processor type before cache restoration in resume Date: Tue, 26 Feb 2013 15:26:53 +0530 Message-Id: <1361872613-12040-1-git-send-email-inderpal.singh@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQkfpSlwbY2BH/AQq1Id4JXfxEiV9Q9B7ohPd3YSIShaWEgrZuO+ddNBalxQDrZFEzAHjXmd Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence check the same before restoring the cache in resume. This is needed for single kernel image. Signed-off-by: Inderpal Singh --- changes in v2: - check processor midr instead of checking all soc ids as suggested by Kukjin arch/arm/mach-exynos/common.c | 4 ++++ arch/arm/plat-samsung/include/plat/pm.h | 1 + arch/arm/plat-samsung/s5p-sleep.S | 10 ++++++++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index c4b2071..5585325 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -53,6 +54,7 @@ #include "common.h" #define L2_AUX_VAL 0x7C470001 #define L2_AUX_MASK 0xC200ffff +#define CPU_MASK 0xff0ffff0 static const char name_exynos4210[] = "EXYNOS4210"; static const char name_exynos4212[] = "EXYNOS4212"; @@ -716,6 +718,8 @@ static int __init exynos4_l2x0_cache_init(void) if (soc_is_exynos5250() || soc_is_exynos5440()) return 0; + cpu_midr = read_cpuid_id() & CPU_MASK; + ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); if (!ret) { l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index f6fcade..532f5d7 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -184,3 +184,4 @@ extern void samsung_pm_save_gpios(void); extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); +extern unsigned long cpu_midr; diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index bdf6dad..3b350d0 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S @@ -25,6 +25,8 @@ #include #include +#define CPU_CORTEX_A9 0x410FC090 + /* * The following code is located into the .data section. This is to * allow l2x0_regs_phys to be accessed with a relative load while we @@ -51,6 +53,11 @@ ENTRY(s3c_cpu_resume) #ifdef CONFIG_CACHE_L2X0 + adr r0, cpu_midr + ldr r1, [r0] + ldr r0, =CPU_CORTEX_A9 + cmp r1, r0 + bne resume_l2on adr r0, l2x0_regs_phys ldr r0, [r0] ldr r1, [r0, #L2X0_R_PHY_BASE] @@ -77,4 +84,7 @@ ENDPROC(s3c_cpu_resume) .globl l2x0_regs_phys l2x0_regs_phys: .long 0 + .globl cpu_midr +cpu_midr: + .long 0 #endif