From patchwork Fri Aug 24 14:52:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 10948 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E782D23F27 for ; Fri, 24 Aug 2012 14:52:30 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id D68B7A18970 for ; Fri, 24 Aug 2012 14:52:12 +0000 (UTC) Received: by iafj25 with SMTP id j25so1253867iaf.11 for ; Fri, 24 Aug 2012 07:52:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=1C0495GHZ8cqoVD+Z10lFGKZfXvvXb7sbDcWIAJpLbk=; b=e8ntlLKH1Xewoq2VBf0s6Ax8MkRO1dT2dmY/ejP4bc5F7hNJF0pu2VAhMHv5BasDgL PajvTE9PxY8qe/72K0LyvP0d8xawfMor4gx/llw4XiHG8DMFG5m30LqYKH5nBi0wbfay ho+YxHcJOapDXDGU5CaOH19A9vqbufIyi3k0Os12tsme6XPr5zLsbxEU+Yk08ST3lGlI n951tpLYuQPee1N4g/0Xo2oSr9E5uxhPbZLDB2ZUsOnFdPFQ+QyJxqanuN77HPEvzNxm muasunEgTuevw2+GbDVV01MZ1XvWHE94oavltWOJw8gSYgX7FLRMSi6h79t5FhRXTICM TISg== Received: by 10.50.207.106 with SMTP id lv10mr2528076igc.0.1345819949752; Fri, 24 Aug 2012 07:52:29 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp323911igc; Fri, 24 Aug 2012 07:52:29 -0700 (PDT) Received: by 10.182.124.102 with SMTP id mh6mr4124670obb.48.1345819948397; Fri, 24 Aug 2012 07:52:28 -0700 (PDT) Received: from mail-pb0-f50.google.com (mail-pb0-f50.google.com [209.85.160.50]) by mx.google.com with ESMTPS id fy3si9760126obc.207.2012.08.24.07.52.27 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Aug 2012 07:52:28 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) client-ip=209.85.160.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) smtp.mail=chander.kashyap@linaro.org Received: by pbcmd12 with SMTP id md12so3801809pbc.37 for ; Fri, 24 Aug 2012 07:52:27 -0700 (PDT) Received: by 10.68.238.166 with SMTP id vl6mr13464120pbc.96.1345819947260; Fri, 24 Aug 2012 07:52:27 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id gv1sm8449469pbc.38.2012.08.24.07.52.25 (version=SSLv3 cipher=OTHER); Fri, 24 Aug 2012 07:52:26 -0700 (PDT) From: Chander Kashyap To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, linux-arm-kernel@lists.infradead.org, patches@linaro.org Subject: [PATCH] ARM: Exynos4: Turn off clocks for NAND, OneNAND and TSI controllers Date: Fri, 24 Aug 2012 20:22:16 +0530 Message-Id: <1345819936-6503-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQkDz33ufsbMJ2WW3ySeTqYpADuPqqYa4hvcGtG+tbJNf8pVlWlPtH7ZwoFJxbHizsG7H+yu The clocks for NAND, OneNAND and Transport Stream Interface(TSI) controllers could be either enabled or disabled at boot. To ensure that these are turned off until used, add them to the list of clocks to be turned off during boot. Signed-off-by: Chander Kashyap Reviewed-by: Thomas Abraham --- arch/arm/mach-exynos/clock-exynos4.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index 2f51293..7cc5491 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -501,6 +501,10 @@ static struct clk exynos4_init_clocks_off[] = { .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 3), }, { + .name = "tsi", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 4), + }, { .name = "hsmmc", .devname = "exynos4-sdhci.0", .parent = &exynos4_clk_aclk_133.clk, @@ -530,6 +534,14 @@ static struct clk exynos4_init_clocks_off[] = { .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 9), }, { + .name = "onenand", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 15), + }, { + .name = "nfcon", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 16), + }, { .name = "dac", .devname = "s5p-sdo", .enable = exynos4_clk_ip_tv_ctrl,