From patchwork Mon Jul 16 05:07:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 9997 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E998423E3D for ; Mon, 16 Jul 2012 05:07:41 +0000 (UTC) Received: from mail-ob0-f180.google.com (mail-ob0-f180.google.com [209.85.214.180]) by fiordland.canonical.com (Postfix) with ESMTP id AFB1AA18832 for ; Mon, 16 Jul 2012 05:07:41 +0000 (UTC) Received: by obbuo19 with SMTP id uo19so9439188obb.11 for ; Sun, 15 Jul 2012 22:07:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=icw1m1EUlxjofeKvdv0QvQXPUQ3HMWU7Icp78IqP3dM=; b=o6C3ckktKm8trUd0okXujojDK+M36kATocY752nHDrXvQFuiQvQlp1vmjiMW8MeO2f rKcvjEDdfBMwaryln4Ol5u4mqigy37vBEq5zjV4O8CHb0kw6WQYe1ZF2oXglJfieNm8c eRaHWsX+ap97KfYLdr59XKKD6wJG2p1IngmCg3VtInZ+kdfrVxl4gTASC+cVC9htlcyy dfy8Asfs9SOhV4q9xVmtOZ6MNX1XfRnhZPhzLZ2caI97Mg+pcDkH+u8V+jLDpe+GCGdZ zXCt85hFK85BeYEG3gNTsQI2DQ30WLym5sWtw7cxnNlNSa4NIcUNkJKZO8q5Fk/Zspw+ 6vTA== Received: by 10.50.46.232 with SMTP id y8mr4269215igm.57.1342415251910; Sun, 15 Jul 2012 22:07:31 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.241.2 with SMTP id lc2csp4896ibb; Sun, 15 Jul 2012 22:07:31 -0700 (PDT) Received: by 10.236.180.130 with SMTP id j2mr8144446yhm.14.1342415251213; Sun, 15 Jul 2012 22:07:31 -0700 (PDT) Received: from mail-yx0-f178.google.com (mail-yx0-f178.google.com [209.85.213.178]) by mx.google.com with ESMTPS id u62si12730995yhd.75.2012.07.15.22.07.31 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Jul 2012 22:07:31 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.213.178 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) client-ip=209.85.213.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.213.178 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) smtp.mail=sachin.kamat@linaro.org Received: by mail-yx0-f178.google.com with SMTP id l6so5473121yen.37 for ; Sun, 15 Jul 2012 22:07:31 -0700 (PDT) Received: by 10.66.76.103 with SMTP id j7mr20011926paw.60.1342415250582; Sun, 15 Jul 2012 22:07:30 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id ru4sm11131865pbc.66.2012.07.15.22.07.28 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Jul 2012 22:07:29 -0700 (PDT) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, sachin.kamat@linaro.org, patches@linaro.org Subject: [PATCH v2 2/2] ARM: EXYNOS: Add G2D related clock entries for SMDK4X12 Date: Mon, 16 Jul 2012 10:37:00 +0530 Message-Id: <1342415220-15497-3-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1342415220-15497-1-git-send-email-sachin.kamat@linaro.org> References: <1342415220-15497-1-git-send-email-sachin.kamat@linaro.org> X-Gm-Message-State: ALoCoQl5wRQBm1V55biYlIkp3qzHqmDTtqwAAvYzZzXXiXyjmqdvFHtIDNXzcj5QKTD1PVmWet9D Adds G2D related clock entries for SMDK4X12 boards. Signed-off-by: Sachin Kamat --- arch/arm/mach-exynos/clock-exynos4212.c | 41 +++++++++++++++++++++++++++++- 1 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c index da397d2..8fba0b5 100644 --- a/arch/arm/mach-exynos/clock-exynos4212.c +++ b/arch/arm/mach-exynos/clock-exynos4212.c @@ -68,12 +68,45 @@ static struct clksrc_clk clk_mout_mpll_user = { .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 }, }; +static struct clksrc_clk exynos4x12_clk_mout_g2d0 = { + .clk = { + .name = "mout_g2d0", + }, + .sources = &exynos4_clkset_mout_g2d0, + .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 }, +}; + +static struct clksrc_clk exynos4x12_clk_mout_g2d1 = { + .clk = { + .name = "mout_g2d1", + }, + .sources = &exynos4_clkset_mout_g2d1, + .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 }, +}; + +static struct clk *exynos4x12_clkset_mout_g2d_list[] = { + [0] = &exynos4x12_clk_mout_g2d0.clk, + [1] = &exynos4x12_clk_mout_g2d1.clk, +}; + +static struct clksrc_sources exynos4x12_clkset_mout_g2d = { + .sources = exynos4x12_clkset_mout_g2d_list, + .nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list), +}; + static struct clksrc_clk *sysclks[] = { &clk_mout_mpll_user, }; static struct clksrc_clk clksrcs[] = { - /* nothing here yet */ + { + .clk = { + .name = "sclk_fimg2d", + }, + .sources = &exynos4x12_clkset_mout_g2d, + .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 }, + }, }; static struct clk init_clocks_off[] = { @@ -102,7 +135,11 @@ static struct clk init_clocks_off[] = { .devname = "exynos-fimc-lite.1", .enable = exynos4212_clk_ip_isp0_ctrl, .ctrlbit = (1 << 3), - } + }, { + .name = "fimg2d", + .enable = exynos4_clk_ip_dmc_ctrl, + .ctrlbit = (1 << 23), + }, }; #ifdef CONFIG_PM_SLEEP