From patchwork Wed Jun 20 04:35:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 9461 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id DAC6023DEB for ; Wed, 20 Jun 2012 04:47:00 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id 779FEA185BA for ; Wed, 20 Jun 2012 04:47:00 +0000 (UTC) Received: by ggnf1 with SMTP id f1so5800814ggn.11 for ; Tue, 19 Jun 2012 21:47:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=NmsEoEAV7AM2pXk4RvLC9Jey2nyXdZb3p+l32yXxvDI=; b=XytGUS9c3mHJWO0wbz86LDZlgyYsXxcDkjXD0ShF/4yLkU1JpzeSPZXxxzQVoUhWsp m6U12HPs7nDykHQDqaxArabY1BzGyqDYQ/iT1ZDo3PAJhkXmiIdh2Sd7xoWjmC65Y6D1 bQNg5CgHZIXPUGoVw1wAxiEp/qoXrZi094+KD5m60U2qShp9LGGzTwmRN0CLrCF5GGR8 YDTVQKqMBPuD+vl5N6j7GCSGB43KLS8nkgsdGAGEtVxK2P8aG0wW85o/udZ04NJKsj4c qD7tiiMni1SprcJlxQi56h31FViaMUk8gljkE2/94oVjGyb59yC3ZBkGdihACATZw6/z +0rw== Received: by 10.50.160.198 with SMTP id xm6mr3367118igb.0.1340167619555; Tue, 19 Jun 2012 21:46:59 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp160931ibb; Tue, 19 Jun 2012 21:46:58 -0700 (PDT) Received: by 10.68.231.8 with SMTP id tc8mr71327554pbc.140.1340167618371; Tue, 19 Jun 2012 21:46:58 -0700 (PDT) Received: from mail-pz0-f50.google.com (mail-pz0-f50.google.com [209.85.210.50]) by mx.google.com with ESMTPS id vh4si21248839pbc.353.2012.06.19.21.46.58 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 19 Jun 2012 21:46:58 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) client-ip=209.85.210.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) smtp.mail=sachin.kamat@linaro.org Received: by danh15 with SMTP id h15so10656576dan.37 for ; Tue, 19 Jun 2012 21:46:58 -0700 (PDT) Received: by 10.68.226.226 with SMTP id rv2mr71873646pbc.101.1340167617954; Tue, 19 Jun 2012 21:46:57 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id wk3sm30459022pbc.21.2012.06.19.21.46.55 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 19 Jun 2012 21:46:57 -0700 (PDT) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, sachin.kamat@linaro.org, patches@linaro.org Subject: [PATCH 1/2][Resend] ARM: EXYNOS: Update HSOTG PHY clock setting for Exynos4x12 Date: Wed, 20 Jun 2012 10:05:16 +0530 Message-Id: <1340166917-25657-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.4.1 X-Gm-Message-State: ALoCoQkDgZPhWkOi5aiezgH+6WWWCHrzy3jYF0e7FJIDOxDvicc2tYKTMLM2p8Js3iqlz8bTk886 Adds clock setting entries for Exynos4212 and Exynos4412 platforms. Signed-off-by: Sachin Kamat --- Based on v3.5-for-usb-2 branch of Kukjin's tree --- arch/arm/mach-exynos/include/mach/regs-usb-phy.h | 20 ++++++-- arch/arm/mach-exynos/setup-usb-phy.c | 55 ++++++++++++++++----- arch/arm/plat-samsung/include/plat/cpu.h | 4 ++ 3 files changed, 61 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h index c337cf3..0727773 100644 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h @@ -35,11 +35,21 @@ #define PHY1_COMMON_ON_N (1 << 7) #define PHY0_COMMON_ON_N (1 << 4) #define PHY0_ID_PULLUP (1 << 2) -#define CLKSEL_MASK (0x3 << 0) -#define CLKSEL_SHIFT (0) -#define CLKSEL_48M (0x0 << 0) -#define CLKSEL_12M (0x2 << 0) -#define CLKSEL_24M (0x3 << 0) + +#define EXYNOS4_CLKSEL_SHIFT (0) + +#define EXYNOS4210_CLKSEL_MASK (0x3 << 0) +#define EXYNOS4210_CLKSEL_48M (0x0 << 0) +#define EXYNOS4210_CLKSEL_12M (0x2 << 0) +#define EXYNOS4210_CLKSEL_24M (0x3 << 0) + +#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0) +#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0) +#define EXYNOS4X12_CLKSEL_10M (0x1 << 0) +#define EXYNOS4X12_CLKSEL_12M (0x2 << 0) +#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0) +#define EXYNOS4X12_CLKSEL_20M (0x4 << 0) +#define EXYNOS4X12_CLKSEL_24M (0x5 << 0) #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c index 1af0a7f..d26deb7 100644 --- a/arch/arm/mach-exynos/setup-usb-phy.c +++ b/arch/arm/mach-exynos/setup-usb-phy.c @@ -31,22 +31,51 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev) struct clk *xusbxti_clk; u32 phyclk; - /* set clock frequency for PLL */ - phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK; xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { - switch (clk_get_rate(xusbxti_clk)) { - case 12 * MHZ: - phyclk |= CLKSEL_12M; - break; - case 24 * MHZ: - phyclk |= CLKSEL_24M; - break; - default: - case 48 * MHZ: - /* default reference clock */ - break; + if (soc_is_exynos4210()) { + /* set clock frequency for PLL */ + phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK; + + switch (clk_get_rate(xusbxti_clk)) { + case 12 * MHZ: + phyclk |= EXYNOS4210_CLKSEL_12M; + break; + default: + case 24 * MHZ: + phyclk |= EXYNOS4210_CLKSEL_24M; + break; + case 48 * MHZ: + phyclk |= EXYNOS4210_CLKSEL_48M; + break; + } + } else if (soc_is_exynos4212() || soc_is_exynos4412()) { + /* set clock frequency for PLL */ + phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK; + + switch (clk_get_rate(xusbxti_clk)) { + case 9600 * KHZ: + phyclk |= EXYNOS4X12_CLKSEL_9600K; + break; + case 10 * MHZ: + phyclk |= EXYNOS4X12_CLKSEL_10M; + break; + case 12 * MHZ: + phyclk |= EXYNOS4X12_CLKSEL_12M; + break; + case 19200 * KHZ: + phyclk |= EXYNOS4X12_CLKSEL_19200K; + break; + case 20 * MHZ: + phyclk |= EXYNOS4X12_CLKSEL_20M; + break; + default: + case 24 * MHZ: + /* default reference clock */ + phyclk |= EXYNOS4X12_CLKSEL_24M; + break; + } } clk_put(xusbxti_clk); } diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 787ceac..6a6ff7e 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } +#ifndef KHZ +#define KHZ (1000) +#endif + #ifndef MHZ #define MHZ (1000*1000) #endif