From patchwork Thu May 24 08:55:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 8940 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 9CC4A23F04 for ; Thu, 24 May 2012 09:05:57 +0000 (UTC) Received: from mail-gh0-f180.google.com (mail-gh0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id 4B520A18493 for ; Thu, 24 May 2012 09:05:57 +0000 (UTC) Received: by ghbz12 with SMTP id z12so2191880ghb.11 for ; Thu, 24 May 2012 02:05:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=5fl9e6S7lmD/kmHL+YRYbmdfWFc8x25bVCjzKEFnpfI=; b=FBBBck5zsG7rAoD/kAo9qTFnNs9EFFs95eQWxCozAX9duDm1gTWk/jquHlux8k/7EO nxYmoHD5eRLtT4UhsiT9anbHw7efpi8MwxiXVyUHaFEnvYUud7ayI2ayB+28RDIcTlbT 5UF/RLiWAl8O8hvw40ZMc7Or1HuD/XLbEDPb7PzY0lZ3inF2MLl7xOKf8QFLQiFYZoGk EeOkLk1ACOJI/Yu+14TpYnEIoGt2rATV/gK2HgggHgx4iqs0hhvQeXmtFM4o++W6wSSm +btD+WSCzbZMkcZebSXSb3CHwqByZAieQGT9YyBcN6Y+n73r5/1lSakNTprEaeK+wwz4 2MGg== Received: by 10.50.185.233 with SMTP id ff9mr15503088igc.57.1337850356382; Thu, 24 May 2012 02:05:56 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp24079ibd; Thu, 24 May 2012 02:05:55 -0700 (PDT) Received: by 10.68.234.200 with SMTP id ug8mr9539766pbc.54.1337850354383; Thu, 24 May 2012 02:05:54 -0700 (PDT) Received: from mail-pz0-f50.google.com (mail-pz0-f50.google.com [209.85.210.50]) by mx.google.com with ESMTPS id pd5si249585pbc.313.2012.05.24.02.05.54 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 24 May 2012 02:05:54 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) client-ip=209.85.210.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) smtp.mail=sachin.kamat@linaro.org Received: by danh15 with SMTP id h15so13031351dan.37 for ; Thu, 24 May 2012 02:05:54 -0700 (PDT) Received: by 10.68.237.166 with SMTP id vd6mr19141206pbc.139.1337850353863; Thu, 24 May 2012 02:05:53 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id u5sm4813662pbu.76.2012.05.24.02.05.51 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 24 May 2012 02:05:52 -0700 (PDT) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, sachin.kamat@linaro.org, patches@linaro.org Subject: [PATCH-Resend 1/2] ARM: EXYNOS: Update HSOTG PHY clock setting for Exynos4x12 Date: Thu, 24 May 2012 14:25:25 +0530 Message-Id: <1337849726-17744-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.4.1 X-Gm-Message-State: ALoCoQlHWdpp+qmtdXLfYqYX22CjL9Fkg5q25utD0YTCXX90U+eOT54MbUvf1r0YLg3I1t22vzOj Adds clock setting entries for Exynos4212 and Exynos4412 platforms. Signed-off-by: Sachin Kamat --- arch/arm/mach-exynos/include/mach/regs-usb-phy.h | 20 ++++++-- arch/arm/mach-exynos/setup-usb-phy.c | 55 ++++++++++++++++----- arch/arm/plat-samsung/include/plat/cpu.h | 4 ++ 3 files changed, 61 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h index c337cf3..0727773 100644 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h @@ -35,11 +35,21 @@ #define PHY1_COMMON_ON_N (1 << 7) #define PHY0_COMMON_ON_N (1 << 4) #define PHY0_ID_PULLUP (1 << 2) -#define CLKSEL_MASK (0x3 << 0) -#define CLKSEL_SHIFT (0) -#define CLKSEL_48M (0x0 << 0) -#define CLKSEL_12M (0x2 << 0) -#define CLKSEL_24M (0x3 << 0) + +#define EXYNOS4_CLKSEL_SHIFT (0) + +#define EXYNOS4210_CLKSEL_MASK (0x3 << 0) +#define EXYNOS4210_CLKSEL_48M (0x0 << 0) +#define EXYNOS4210_CLKSEL_12M (0x2 << 0) +#define EXYNOS4210_CLKSEL_24M (0x3 << 0) + +#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0) +#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0) +#define EXYNOS4X12_CLKSEL_10M (0x1 << 0) +#define EXYNOS4X12_CLKSEL_12M (0x2 << 0) +#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0) +#define EXYNOS4X12_CLKSEL_20M (0x4 << 0) +#define EXYNOS4X12_CLKSEL_24M (0x5 << 0) #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c index 1af0a7f..8f90ce0 100644 --- a/arch/arm/mach-exynos/setup-usb-phy.c +++ b/arch/arm/mach-exynos/setup-usb-phy.c @@ -31,22 +31,51 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev) struct clk *xusbxti_clk; u32 phyclk; - /* set clock frequency for PLL */ - phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK; xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { - switch (clk_get_rate(xusbxti_clk)) { - case 12 * MHZ: - phyclk |= CLKSEL_12M; - break; - case 24 * MHZ: - phyclk |= CLKSEL_24M; - break; - default: - case 48 * MHZ: - /* default reference clock */ - break; + if (soc_is_exynos4210()) { + /* set clock frequency for PLL */ + phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK; + + switch (clk_get_rate(xusbxti_clk)) { + case 12 * MHZ: + phyclk |= EXYNOS4210_CLKSEL_12M; + break; + case 24 * MHZ: + phyclk |= EXYNOS4210_CLKSEL_24M; + break; + default: + case 48 * MHZ: + /* default reference clock */ + break; + } + } else if (soc_is_exynos4212() || soc_is_exynos4412()) { + /* set clock frequency for PLL */ + phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK; + + switch (clk_get_rate(xusbxti_clk)) { + case 9600 * KHZ: + phyclk |= EXYNOS4X12_CLKSEL_9600K; + break; + case 10 * MHZ: + phyclk |= EXYNOS4X12_CLKSEL_10M; + break; + case 12 * MHZ: + phyclk |= EXYNOS4X12_CLKSEL_12M; + break; + case 19200 * KHZ: + phyclk |= EXYNOS4X12_CLKSEL_19200K; + break; + case 20 * MHZ: + phyclk |= EXYNOS4X12_CLKSEL_20M; + break; + default: + case 24 * MHZ: + /* default reference clock */ + phyclk |= EXYNOS4X12_CLKSEL_24M; + break; + } } clk_put(xusbxti_clk); } diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 787ceac..6a6ff7e 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } +#ifndef KHZ +#define KHZ (1000) +#endif + #ifndef MHZ #define MHZ (1000*1000) #endif