From patchwork Fri May 18 04:07:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 8783 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 4E30F23E49 for ; Fri, 18 May 2012 04:18:11 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 1F1B8A18BCF for ; Fri, 18 May 2012 04:18:11 +0000 (UTC) Received: by mail-yx0-f180.google.com with SMTP id q6so3061718yen.11 for ; Thu, 17 May 2012 21:18:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=fCcE6A++jxWhLasHl5vs7TwQCckxfPIO7LI/czd1A5I=; b=Ue8mrL2kCOy6i1ACblG2QnOQXpAMw7gBqZ6smSZ1g2WPvnt2vD2LqOXTjhmPpetWDV 9eyeKHqpEMnVlBQwek8ar7o33jzif1XymZ1xEnQODpnJN2QDKJDqBy3lTa6jdKwPtmHJ y/1pYbwXHAhPSkpoIg0HgtEXs/42BMDSvN8lyieYCoORHo1KkVVKU5+MUVMORYLa+M04 NBYobfpIcnesdnMtknzw8BTtOD6zwdqAg/z43j5LjOEjR6OzZBm+tH288s+F3X2D3TAX mr8KKVbwkY+FXVTVD9tgdO//4N9em371zx/UXXSKYpfGbuax2cpgcuGbdMwzB2IYcjMX zIRQ== Received: by 10.50.163.99 with SMTP id yh3mr7300166igb.53.1337314690718; Thu, 17 May 2012 21:18:10 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp73879ibd; Thu, 17 May 2012 21:18:10 -0700 (PDT) Received: by 10.68.129.198 with SMTP id ny6mr20666529pbb.22.1337314689950; Thu, 17 May 2012 21:18:09 -0700 (PDT) Received: from mail-pb0-f50.google.com (mail-pb0-f50.google.com [209.85.160.50]) by mx.google.com with ESMTPS id pb10si14134938pbc.256.2012.05.17.21.18.09 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 17 May 2012 21:18:09 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) client-ip=209.85.160.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) smtp.mail=sachin.kamat@linaro.org Received: by pbbrr4 with SMTP id rr4so4110650pbb.37 for ; Thu, 17 May 2012 21:18:09 -0700 (PDT) Received: by 10.68.132.232 with SMTP id ox8mr6678770pbb.145.1337314689634; Thu, 17 May 2012 21:18:09 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id vc4sm11387119pbc.8.2012.05.17.21.18.06 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 17 May 2012 21:18:08 -0700 (PDT) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, sachin.kamat@linaro.org, patches@linaro.org Subject: [PATCH 2/2] ARM: EXYNOS: Add G2D related clock entries for SMDK4X12 Date: Fri, 18 May 2012 09:37:51 +0530 Message-Id: <1337314071-15305-3-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1337314071-15305-1-git-send-email-sachin.kamat@linaro.org> References: <1337314071-15305-1-git-send-email-sachin.kamat@linaro.org> X-Gm-Message-State: ALoCoQm/vu/zV6lp8rZziJvXZ5+NgXCF2bdIjzVsp/cu9CbHSW9sHtSmhgcmRpF8o4Wtn3SwWAwB Adds G2D related clock entries for SMDK4X12 boards. Signed-off-by: Sachin Kamat --- arch/arm/mach-exynos/clock-exynos4212.c | 41 +++++++++++++++++++++++++++++- 1 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c index da397d2..fdc26ac 100644 --- a/arch/arm/mach-exynos/clock-exynos4212.c +++ b/arch/arm/mach-exynos/clock-exynos4212.c @@ -68,12 +68,45 @@ static struct clksrc_clk clk_mout_mpll_user = { .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 }, }; +static struct clksrc_clk exynos4_clk_mout_g2d0 = { + .clk = { + .name = "mout_g2d0", + }, + .sources = &exynos4_clkset_mout_g2d0, + .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 }, +}; + +static struct clksrc_clk exynos4_clk_mout_g2d1 = { + .clk = { + .name = "mout_g2d1", + }, + .sources = &exynos4_clkset_mout_g2d1, + .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 }, +}; + +static struct clk *exynos4_clkset_mout_g2d_list[] = { + [0] = &exynos4_clk_mout_g2d0.clk, + [1] = &exynos4_clk_mout_g2d1.clk, +}; + +static struct clksrc_sources exynos4_clkset_mout_g2d = { + .sources = exynos4_clkset_mout_g2d_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list), +}; + static struct clksrc_clk *sysclks[] = { &clk_mout_mpll_user, }; static struct clksrc_clk clksrcs[] = { - /* nothing here yet */ + { + .clk = { + .name = "sclk_fimg2d", + }, + .sources = &exynos4_clkset_mout_g2d, + .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 }, + }, }; static struct clk init_clocks_off[] = { @@ -102,7 +135,11 @@ static struct clk init_clocks_off[] = { .devname = "exynos-fimc-lite.1", .enable = exynos4212_clk_ip_isp0_ctrl, .ctrlbit = (1 << 3), - } + }, { + .name = "fimg2d", + .enable = exynos4_clk_ip_dmc_ctrl, + .ctrlbit = (1 << 23), + }, }; #ifdef CONFIG_PM_SLEEP