From patchwork Thu Mar 29 03:25:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inderpal Singh X-Patchwork-Id: 7514 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2D86023E12 for ; Thu, 29 Mar 2012 03:25:37 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id C2452A183B4 for ; Thu, 29 Mar 2012 03:25:36 +0000 (UTC) Received: by iage36 with SMTP id e36so3245755iag.11 for ; Wed, 28 Mar 2012 20:25:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-forwarded-to:x-forwarded-for:delivered-to :received-spf:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=Y5TiBYzgfOSRpteHvMNec+WkLRtzdX3nFJiLfpg7XuQ=; b=MCeAVIwhP4cK02q323SVYIT2ShdvTrYyMfpJiFnpsyPnBqw3h0WJZCG8+i7jzKqCSJ AGZ4Sa4hrSy7r216DtavXn4fNpRGFIg5qMoI5Uv/VXT/fHA56mayihCksJE0kR5dwyju IbxoMgGJXZBFqAbDU0B+HP8w8PaUhs08X1MDJU7aiROQ+mDvPojWRiy1yBDo57TM/8LA MqqXIuoUFwOtTlLQOHWaMVHguz0rZedeBubMmmB71r4Gbz680xCiyWfAi71YV1ORNv10 P3ogn1FXUneNF5ZVjkyMp/xRm0kLDtTKgJ9j45LnpiHb4zUJHyM2uxVdOMKfoU4RVzK2 mXMw== MIME-Version: 1.0 Received: by 10.50.194.226 with SMTP id hz2mr270164igc.44.1332991536145; Wed, 28 Mar 2012 20:25:36 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp19340ibw; Wed, 28 Mar 2012 20:25:35 -0700 (PDT) Received: by 10.100.212.4 with SMTP id k4mr10110277ang.35.1332991534922; Wed, 28 Mar 2012 20:25:34 -0700 (PDT) Received: from mail-gx0-f178.google.com (mail-gx0-f178.google.com [209.85.161.178]) by mx.google.com with ESMTPS id d67si5123378yhh.141.2012.03.28.20.25.34 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 28 Mar 2012 20:25:34 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.161.178 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) client-ip=209.85.161.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.161.178 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) smtp.mail=inderpal.singh@linaro.org Received: by ggno1 with SMTP id o1so1441876ggn.37 for ; Wed, 28 Mar 2012 20:25:34 -0700 (PDT) Received: by 10.68.136.41 with SMTP id px9mr1879327pbb.147.1332991534087; Wed, 28 Mar 2012 20:25:34 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id f2sm4023989pbr.16.2012.03.28.20.25.31 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 28 Mar 2012 20:25:33 -0700 (PDT) From: Inderpal Singh To: samsung@lists.linaro.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, kgene.kim@samsung.com, Inderpal Singh Subject: [PATCH] ARM: EXYNOS4: Support Suspend/Resume for EXYNOS4412 Date: Thu, 29 Mar 2012 08:55:17 +0530 Message-Id: <1332991517-3083-1-git-send-email-inderpal.singh@linaro.org> X-Mailer: git-send-email 1.7.5.4 X-Gm-Message-State: ALoCoQm4bw8Frmoyk1WCYbqJIGp5aBYwIZ/WkgNy3xCohdvNuan1ha4JFT0Hce15ZLvuLDFG2GjM This patch provides the suspend/resume support for EXYNOS4412. Signed-off-by: Inderpal Singh --- arch/arm/mach-exynos/include/mach/regs-pmu.h | 10 +++++++++- arch/arm/mach-exynos/pm.c | 2 +- arch/arm/mach-exynos/pmu.c | 24 ++++++++++++++++++++---- 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index 4c53f38..606b199 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -177,7 +177,7 @@ #define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) -/* Only for EXYNOS4212 */ +/* Only for EXYNOS4x12 */ #define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) @@ -218,4 +218,12 @@ #define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) #define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) +/* Only for EXYNOS4412 */ +#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020) +#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024) +#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028) +#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030) +#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034) +#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038) + #endif /* __ASM_ARCH_REGS_PMU_H */ diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 428cfeb..f0bb467 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -313,7 +313,7 @@ static int exynos4_pm_suspend(void) tmp &= ~S5P_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); - if (soc_is_exynos4212()) { + if (soc_is_exynos4212() || soc_is_exynos4412()) { tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION); tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM | S5P_USE_STANDBYWFE_ISP_ARM); diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index bba48f5..77c6815 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = { { PMU_TABLE_END,}, }; -static struct exynos4_pmu_conf exynos4212_pmu_config[] = { +static struct exynos4_pmu_conf exynos4x12_pmu_config[] = { { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, @@ -202,6 +202,16 @@ static struct exynos4_pmu_conf exynos4212_pmu_config[] = { { PMU_TABLE_END,}, }; +static struct exynos4_pmu_conf exynos4412_pmu_config[] = { + { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, + { S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } }, + { PMU_TABLE_END,}, +}; + void exynos4_sys_powerdown_conf(enum sys_powerdown mode) { unsigned int i; @@ -209,6 +219,12 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode) for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++) __raw_writel(exynos4_pmu_config[i].val[mode], exynos4_pmu_config[i].reg); + + if (soc_is_exynos4412()) { + for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++) + __raw_writel(exynos4412_pmu_config[i].val[mode], + exynos4412_pmu_config[i].reg); + } } static int __init exynos4_pmu_init(void) @@ -218,9 +234,9 @@ static int __init exynos4_pmu_init(void) if (soc_is_exynos4210()) { exynos4_pmu_config = exynos4210_pmu_config; pr_info("EXYNOS4210 PMU Initialize\n"); - } else if (soc_is_exynos4212()) { - exynos4_pmu_config = exynos4212_pmu_config; - pr_info("EXYNOS4212 PMU Initialize\n"); + } else if (soc_is_exynos4212() || soc_is_exynos4412()) { + exynos4_pmu_config = exynos4x12_pmu_config; + pr_info("EXYNOS4x12 PMU Initialize\n"); } else { pr_info("EXYNOS4: PMU not supported\n"); }