From patchwork Tue Feb 21 06:19:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 6853 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id CA88923EB0 for ; Tue, 21 Feb 2012 06:21:53 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 8B18FA185A5 for ; Tue, 21 Feb 2012 06:21:53 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id z7so11912584iab.11 for ; Mon, 20 Feb 2012 22:21:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:x-forwarded-to:x-forwarded-for:delivered-to :received-spf:dkim-signature:sender:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=KjPsQUfv5+PnHUbt9XreLqc4rXrGN+f4uLV1XdXDUX8=; b=tMHF5sC7iMo5XX5GEBO2NlD7SdaRMKWU3pETZOFmAbdtYNNOxBW376vX6Ba2RRomr4 C1DtmC4ySD6jidVCD9YRfQc0I9c3sJevVrhhnFVWGD+C4DOtpXG0OcZlIoVi3YgQ7JX0 kI/NBrY6nxypWfKcFFpp/F9qvx0qYrBe/a/hs= MIME-Version: 1.0 Received: by 10.50.89.232 with SMTP id br8mr13931632igb.30.1329805313365; Mon, 20 Feb 2012 22:21:53 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.11.10 with SMTP id r10csp80757ibr; Mon, 20 Feb 2012 22:21:52 -0800 (PST) Received: by 10.68.216.132 with SMTP id oq4mr59184637pbc.41.1329805312658; Mon, 20 Feb 2012 22:21:52 -0800 (PST) Received: from mail-pz0-f50.google.com (mail-pz0-f50.google.com [209.85.210.50]) by mx.google.com with ESMTPS id h6si23059882pbn.214.2012.02.20.22.21.51 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 20 Feb 2012 22:21:52 -0800 (PST) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.50 as permitted sender) client-ip=209.85.210.50; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.50 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass header.i=@gmail.com Received: by mail-pz0-f50.google.com with SMTP id d2so5431210dal.37 for ; Mon, 20 Feb 2012 22:21:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=KjPsQUfv5+PnHUbt9XreLqc4rXrGN+f4uLV1XdXDUX8=; b=pNU0ONvdQAoh3d5u/gHomYos8cdLQ78WR/o5vBZ/nVGSgMQoXZhArNiM4UeZVO9ndG t1rMJSgJUVgahMlnuJCSwnxU+mTJR8Akr4FzQ9gVebUlgOsnm+CXNjuTdF3THFBQ8ptN VuOsILWlJBKx5iUOUV4oAqy5bzLy1GmM0h+HM= Received: by 10.68.202.40 with SMTP id kf8mr52938278pbc.153.1329805311819; Mon, 20 Feb 2012 22:21:51 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id vy2sm7541182pbb.48.2012.02.20.22.21.49 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 20 Feb 2012 22:21:51 -0800 (PST) Sender: amit kachhap From: Amit Daniel Kachhap To: kgene.kim@samsung.com, linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, amit.kachhap@linaro.org, patches@linaro.org Subject: [PATCH V6 4/5] ARM: exynos: remove useless code to save/restore L2 Date: Tue, 21 Feb 2012 11:49:49 +0530 Message-Id: <1329805190-8874-5-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1329805190-8874-1-git-send-email-amit.kachhap@linaro.org> References: <1329805190-8874-1-git-send-email-amit.kachhap@linaro.org> X-Gm-Message-State: ALoCoQkELG6Cxj2BR//3kIY/JCTYvkDkbFd0BYGed81bMlfLHKJ0Tv6J+y5c37V78kdrhByym/L+ Following the merge of CPU PM notifiers and L2 resume code, this patch removes useless code to save and restore L2 registers. This is now automatically covered by suspend calls which integrated CPU PM notifiers and new sleep code that allows to resume L2 before MMU is turned on. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap --- arch/arm/mach-exynos/pm.c | 15 --------------- 1 files changed, 0 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index e190130..4816827 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -155,13 +155,6 @@ static struct sleep_save exynos4_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), }; -static struct sleep_save exynos4_l2cc_save[] = { - SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), -}; /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; @@ -182,7 +175,6 @@ static void exynos4_pm_prepare(void) u32 tmp; s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); - s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); @@ -388,13 +380,6 @@ static void exynos4_pm_resume(void) scu_enable(S5P_VA_SCU); #endif -#ifdef CONFIG_CACHE_L2X0 - s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); - outer_inv_all(); - /* enable L2X0*/ - writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); -#endif - early_wakeup: return; }