From patchwork Mon Dec 5 11:06:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 5455 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 45D5023E16 for ; Mon, 5 Dec 2011 11:06:15 +0000 (UTC) Received: from mail-lpp01m010-f52.google.com (mail-lpp01m010-f52.google.com [209.85.215.52]) by fiordland.canonical.com (Postfix) with ESMTP id 2BBC7A18240 for ; Mon, 5 Dec 2011 11:06:15 +0000 (UTC) Received: by mail-lpp01m010-f52.google.com with SMTP id m6so86412lag.11 for ; Mon, 05 Dec 2011 03:06:15 -0800 (PST) Received: by 10.152.104.206 with SMTP id gg14mr5620308lab.41.1323083175068; Mon, 05 Dec 2011 03:06:15 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs250944lal; Mon, 5 Dec 2011 03:06:14 -0800 (PST) Received: by 10.236.155.170 with SMTP id j30mr10255138yhk.56.1323083172924; Mon, 05 Dec 2011 03:06:12 -0800 (PST) Received: from mail-yw0-f50.google.com (mail-yw0-f50.google.com [209.85.213.50]) by mx.google.com with ESMTPS id 24si14284233yhs.41.2011.12.05.03.06.12 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 05 Dec 2011 03:06:12 -0800 (PST) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.213.50 as permitted sender) client-ip=209.85.213.50; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.213.50 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by ywb26 with SMTP id 26so4696114ywb.37 for ; Mon, 05 Dec 2011 03:06:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=Q39EuHxvrhSurnbJF6+hfr/+TzqPSmEbbDs98PqykLk=; b=Q4HipOW/0aK5bpleUQzXxLiqJEBV17GE93vuBYcg/mk/724q14MPTeBXPSf3bfeO0h lSKL9sbaBnuWWWiuiLg2Y7wDGx/UIlC4pJ/iot9MZsT+qExKgUw6pjNUzp+wqdCCOOor bRniOtKIvFffl+r3UlHLG2FIAKA5ttSZcLbu4= Received: by 10.50.216.137 with SMTP id oq9mr9831158igc.40.1323083172312; Mon, 05 Dec 2011 03:06:12 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id ds5sm9955545ibb.5.2011.12.05.03.06.09 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 05 Dec 2011 03:06:11 -0800 (PST) Sender: amit kachhap From: Amit Daniel Kachhap To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, linux-arm-kernel@lists.infradead.org, amit.kachhap@linaro.org, patches@linaro.org Subject: [PATCH V4 4/5] ARM: exynos: remove useless code to save/restore L2 Date: Mon, 5 Dec 2011 16:36:11 +0530 Message-Id: <1323083172-14096-5-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1323083172-14096-1-git-send-email-amit.kachhap@linaro.org> References: <1323083172-14096-1-git-send-email-amit.kachhap@linaro.org> Following the merge of CPU PM notifiers and L2 resume code, this patch removes useless code to save and restore L2 registers. This is now automatically covered by suspend calls which integrated CPU PM notifiers and new sleep code that allows to resume L2 before MMU is turned on. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap --- arch/arm/mach-exynos/pm.c | 15 --------------- 1 files changed, 0 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 4093fea..1883cc9 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -155,13 +155,6 @@ static struct sleep_save exynos4_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), }; -static struct sleep_save exynos4_l2cc_save[] = { - SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), -}; /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; @@ -182,7 +175,6 @@ static void exynos4_pm_prepare(void) u32 tmp; s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); - s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); @@ -384,13 +376,6 @@ static void exynos4_pm_resume(void) scu_enable(S5P_VA_SCU); -#ifdef CONFIG_CACHE_L2X0 - s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); - outer_inv_all(); - /* enable L2X0*/ - writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); -#endif - early_wakeup: return; }