From patchwork Mon Dec 5 11:06:10 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 5454 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 110FF23E16 for ; Mon, 5 Dec 2011 11:06:13 +0000 (UTC) Received: from mail-lpp01m010-f52.google.com (mail-lpp01m010-f52.google.com [209.85.215.52]) by fiordland.canonical.com (Postfix) with ESMTP id EAB7FA18240 for ; Mon, 5 Dec 2011 11:06:12 +0000 (UTC) Received: by mail-lpp01m010-f52.google.com with SMTP id m6so86412lag.11 for ; Mon, 05 Dec 2011 03:06:12 -0800 (PST) Received: by 10.152.144.73 with SMTP id sk9mr5567879lab.34.1323083172839; Mon, 05 Dec 2011 03:06:12 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs250941lal; Mon, 5 Dec 2011 03:06:11 -0800 (PST) Received: by 10.43.50.67 with SMTP id vd3mr9239749icb.10.1323083169674; Mon, 05 Dec 2011 03:06:09 -0800 (PST) Received: from mail-iy0-f178.google.com (mail-iy0-f178.google.com [209.85.210.178]) by mx.google.com with ESMTPS id o2si9063665icz.54.2011.12.05.03.06.09 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 05 Dec 2011 03:06:09 -0800 (PST) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.178 as permitted sender) client-ip=209.85.210.178; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.178 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by mail-iy0-f178.google.com with SMTP id j37so3603777iag.37 for ; Mon, 05 Dec 2011 03:06:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=p2cK145yIK2zHFvLaQJwZqJIkYmthys7yCSYZLbI59U=; b=W1tEMtkJeKE4sQREDM5/n/DLjCy0ZAmiN08VsMVFQU3eOei7a+gyymbzd5mo9yHSrD qy1WDE86SYJ4N/akYjZt1UYxDiuE/r7Ge9RF7H780neWYGEhsGHb+s1ZM8lj/M3d977/ nwLl9B+WUN/oU2pRejKtFbRATWTy6uWPXFPK4= Received: by 10.42.154.7 with SMTP id o7mr9753458icw.48.1323083168997; Mon, 05 Dec 2011 03:06:08 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id ds5sm9955545ibb.5.2011.12.05.03.06.05 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 05 Dec 2011 03:06:08 -0800 (PST) Sender: amit kachhap From: Amit Daniel Kachhap To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, linux-arm-kernel@lists.infradead.org, amit.kachhap@linaro.org, patches@linaro.org Subject: [PATCH V4 3/5] ARM: s5p: add L2 early resume code Date: Mon, 5 Dec 2011 16:36:10 +0530 Message-Id: <1323083172-14096-4-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1323083172-14096-1-git-send-email-amit.kachhap@linaro.org> References: <1323083172-14096-1-git-send-email-amit.kachhap@linaro.org> This patch adds code to resume L2 before MMU is enabled in suspend and cpuidle resume paths. s3c_cpu_resume is moved to the data section with appropriate comments. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap --- arch/arm/plat-s5p/sleep.S | 44 ++++++++++++++++++++++++++++++++++++++------ 1 files changed, 38 insertions(+), 6 deletions(-) diff --git a/arch/arm/plat-s5p/sleep.S b/arch/arm/plat-s5p/sleep.S index 0fd591b..006bd01 100644 --- a/arch/arm/plat-s5p/sleep.S +++ b/arch/arm/plat-s5p/sleep.S @@ -23,9 +23,18 @@ */ #include -#include +#include +#include - .text +/* + * The following code is located into the .data section. This is to + * allow l2x0_regs_phys to be accessed with a relative load while we + * can't rely on any MMU translation. We could have put l2x0_regs_phys + * in the .text section as well, but some setups might insist on it to + * be truly read-only. (Reference from: arch/arm/kernel/sleep.S) + */ + .data + .align /* * sleep magic, to allow the bootloader to check for an valid @@ -39,11 +48,34 @@ * s3c_cpu_resume * * resume code entry for bootloader to call - * - * we must put this code here in the data segment as we have no - * other way of restoring the stack pointer after sleep, and we - * must not write to the code segment (code is read-only) */ ENTRY(s3c_cpu_resume) +#ifdef CONFIG_CACHE_L2X0 + adr r0, l2x0_regs_phys + ldr r0, [r0] + ldr r1, [r0, #L2X0_R_PHY_BASE] + ldr r2, [r1, #L2X0_CTRL] + tst r2, #0x1 + bne resume_l2on + ldr r2, [r0, #L2X0_R_AUX_CTRL] + str r2, [r1, #L2X0_AUX_CTRL] + ldr r2, [r0, #L2X0_R_TAG_LATENCY] + str r2, [r1, #L2X0_TAG_LATENCY_CTRL] + ldr r2, [r0, #L2X0_R_DATA_LATENCY] + str r2, [r1, #L2X0_DATA_LATENCY_CTRL] + ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] + str r2, [r1, #L2X0_PREFETCH_CTRL] + ldr r2, [r0, #L2X0_R_PWR_CTRL] + str r2, [r1, #L2X0_POWER_CTRL] + mov r2, #1 + str r2, [r1, #L2X0_CTRL] +resume_l2on: +#endif b cpu_resume +ENDPROC(s3c_cpu_resume) +#ifdef CONFIG_CACHE_L2X0 + .globl l2x0_regs_phys +l2x0_regs_phys: + .long 0 +#endif