From patchwork Tue Nov 22 09:35:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 5270 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 02BAE23E10 for ; Tue, 22 Nov 2011 09:38:18 +0000 (UTC) Received: from mail-gy0-f180.google.com (mail-gy0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id C6624A186DA for ; Tue, 22 Nov 2011 09:38:17 +0000 (UTC) Received: by ghbg18 with SMTP id g18so2922459ghb.11 for ; Tue, 22 Nov 2011 01:38:17 -0800 (PST) Received: by 10.152.104.1 with SMTP id ga1mr11181074lab.40.1321954696627; Tue, 22 Nov 2011 01:38:16 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs169506lal; Tue, 22 Nov 2011 01:38:16 -0800 (PST) Received: by 10.236.128.226 with SMTP id f62mr24668323yhi.104.1321954694570; Tue, 22 Nov 2011 01:38:14 -0800 (PST) Received: from mail-yx0-f178.google.com (mail-yx0-f178.google.com [209.85.213.178]) by mx.google.com with ESMTPS id o21si1855ybc.96.2011.11.22.01.38.13 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 Nov 2011 01:38:14 -0800 (PST) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.213.178 as permitted sender) client-ip=209.85.213.178; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.213.178 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by yenm9 with SMTP id m9so5276635yen.37 for ; Tue, 22 Nov 2011 01:38:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=iSxdnZSo3WqP6+1DVxg5RTs5J97FKwMojz6DtUDhf7A=; b=HqgfvNPn1TYfKvUlnB0sAtlXoAqh/xVa5iOo7i6wciFSUNWGmo5UnW7+KOo4XpUJmE 7YMiXnYAAyv3WSc7gqU97u2+mHFqQXtLQp0jhTMZp2ieUP/a8/cR2UA93EdUNycoP/eL tlzhNM6jL18FoFwNRILAXUWS+7T5i0GBM2Rik= Received: by 10.50.10.163 with SMTP id j3mr11536254igb.15.1321954693440; Tue, 22 Nov 2011 01:38:13 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id el2sm10208537ibb.10.2011.11.22.01.38.02 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 Nov 2011 01:38:12 -0800 (PST) Sender: amit kachhap From: Amit Daniel Kachhap To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, amit.kachhap@linaro.org, patches@linaro.org Subject: [PATCH V3 3/6] ARM: exynos: save L2 settings during bootup Date: Tue, 22 Nov 2011 15:05:29 +0530 Message-Id: <1321954532-18724-4-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1321954532-18724-1-git-send-email-amit.kachhap@linaro.org> References: <1321954532-18724-1-git-send-email-amit.kachhap@linaro.org> This patch adds code to save L2 register configuration at boot, and later used to resume L2 before MMU is enabled in suspend and cpuidle resume paths. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap --- arch/arm/mach-exynos/cpu.c | 42 +++++++++++++++++++++++++++++++----------- 1 files changed, 31 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c index 8e09f34..252e346 100644 --- a/arch/arm/mach-exynos/cpu.c +++ b/arch/arm/mach-exynos/cpu.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -34,6 +35,7 @@ #include #include +#include unsigned int gic_bank_offset __read_mostly; @@ -297,20 +299,38 @@ core_initcall(exynos4_core_init); #ifdef CONFIG_CACHE_L2X0 static int __init exynos4_l2x0_cache_init(void) { - /* TAG, Data Latency Control: 2cycle */ - __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { + l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; + /* TAG, Data Latency Control: 2 cycles */ + l2x0_saved_regs.tag_latency = 0x110; - if (soc_is_exynos4210()) - __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - else if (soc_is_exynos4212() || soc_is_exynos4412()) - __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + if (soc_is_exynos4212() || soc_is_exynos4412()) + l2x0_saved_regs.data_latency = 0x120; + else + l2x0_saved_regs.data_latency = 0x110; + + l2x0_saved_regs.prefetch_ctrl = 0x30000007; + l2x0_saved_regs.pwr_ctrl = + (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN); + + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); - /* L2X0 Prefetch Control */ - __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + __raw_writel(l2x0_saved_regs.tag_latency, + S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + __raw_writel(l2x0_saved_regs.data_latency, + S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - /* L2X0 Power Control */ - __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, - S5P_VA_L2CC + L2X0_POWER_CTRL); + /* L2X0 Prefetch Control */ + __raw_writel(l2x0_saved_regs.prefetch_ctrl, + S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + + /* L2X0 Power Control */ + __raw_writel(l2x0_saved_regs.pwr_ctrl, + S5P_VA_L2CC + L2X0_POWER_CTRL); + + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); + clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); + } l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);