From patchwork Fri Nov 11 06:29:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 5058 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 4CA3B23E01 for ; Fri, 11 Nov 2011 06:30:26 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 417F1A1838B for ; Fri, 11 Nov 2011 06:30:26 +0000 (UTC) Received: by faan26 with SMTP id n26so5311063faa.11 for ; Thu, 10 Nov 2011 22:30:26 -0800 (PST) Received: by 10.152.135.166 with SMTP id pt6mr6131019lab.26.1320993026031; Thu, 10 Nov 2011 22:30:26 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.40.7 with SMTP id t7cs37421lak; Thu, 10 Nov 2011 22:30:25 -0800 (PST) Received: by 10.68.74.40 with SMTP id q8mr21655429pbv.36.1320993023690; Thu, 10 Nov 2011 22:30:23 -0800 (PST) Received: from mail-pz0-f42.google.com (mail-pz0-f42.google.com [209.85.210.42]) by mx.google.com with ESMTPS id jk8si14092403pbc.154.2011.11.10.22.30.22 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 10 Nov 2011 22:30:23 -0800 (PST) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.42 as permitted sender) client-ip=209.85.210.42; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.42 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by pzk36 with SMTP id 36so3535918pzk.1 for ; Thu, 10 Nov 2011 22:30:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=76L+T5aiy6qStLa3Au4A2NlztJPvuDEFwQ5tslqXNNA=; b=d1oYb/3VGkht/bGadk2JZdR7JTSYqt+Zo59freYGzCItoYsSfoMu6M/husbCoddcO5 U9rMWsURXO9JjaXUJkMwWNmc5d8PAiy4/breidKn4LwFc8cQsmoUot/vsC2DmnDx3/pC dNc72NUgLSpNl7drtmXcZnTspJPUOruxxMfmg= Received: by 10.68.16.3 with SMTP id b3mr21132098pbd.86.1320993022752; Thu, 10 Nov 2011 22:30:22 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id jm5sm27653704pbc.1.2011.11.10.22.30.19 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 10 Nov 2011 22:30:22 -0800 (PST) Sender: amit kachhap From: Amit Daniel Kachhap To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, amit.kachhap@linaro.org, patches@linaro.org Subject: [PATCH V2 4/5] ARM: exynos4: remove useless code to save/restore L2 Date: Fri, 11 Nov 2011 11:59:36 +0530 Message-Id: <1320992977-11589-5-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1320992977-11589-1-git-send-email-amit.kachhap@linaro.org> References: <1320992977-11589-1-git-send-email-amit.kachhap@linaro.org> Following the merge of CPU PM notifiers and L2 resume code, this patch removes useless code to save and restore L2 registers. This is now automatically covered by suspend calls which integrated CPU PM notifiers and new sleep code that allows to resume L2 before MMU is turned on. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap --- arch/arm/mach-exynos/pm.c | 15 --------------- 1 files changed, 0 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 509a435..0c264e1 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -154,13 +154,6 @@ static struct sleep_save exynos4_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), }; -static struct sleep_save exynos4_l2cc_save[] = { - SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), -}; /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; @@ -181,7 +174,6 @@ static void exynos4_pm_prepare(void) u32 tmp; s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); - s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); @@ -404,13 +396,6 @@ static void exynos4_pm_resume(void) exynos4_scu_enable(S5P_VA_SCU); -#ifdef CONFIG_CACHE_L2X0 - s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); - outer_inv_all(); - /* enable L2X0*/ - writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); -#endif - early_wakeup: return; }