From patchwork Fri Nov 4 17:03:47 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 4939 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3235723EF9 for ; Fri, 4 Nov 2011 17:04:15 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 25528A18154 for ; Fri, 4 Nov 2011 17:04:15 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id n26so4167205faa.11 for ; Fri, 04 Nov 2011 10:04:15 -0700 (PDT) Received: by 10.152.105.67 with SMTP id gk3mr1133578lab.48.1320426254986; Fri, 04 Nov 2011 10:04:14 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.14.103 with SMTP id o7cs133656lac; Fri, 4 Nov 2011 10:04:14 -0700 (PDT) Received: by 10.236.77.232 with SMTP id d68mr21017455yhe.98.1320426252376; Fri, 04 Nov 2011 10:04:12 -0700 (PDT) Received: from mail-yw0-f50.google.com (mail-yw0-f50.google.com [209.85.213.50]) by mx.google.com with ESMTPS id o26si12265936yhn.145.2011.11.04.10.04.11 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Nov 2011 10:04:12 -0700 (PDT) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.213.50 as permitted sender) client-ip=209.85.213.50; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.213.50 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by ywa8 with SMTP id 8so3097504ywa.37 for ; Fri, 04 Nov 2011 10:04:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=sFMhoqACqjUActkM/SE6GRO8mB8LM1nSXrhd4E0CspA=; b=amlRoa7fF7xchfkZAnjUi60qKm8XAk2tSly2q1Q3res1H9oml2ukpTujLY9Wra20EM bkca8m0E7jFDOKPjrR0AdqTflQRYmOqBtR9dFp5wQ/Ih2EK1SnFYyVXhmvTZRASdYGJX 0ZQ1SfWb0dsomS7uL6uNFWwYTN7Ly/6eubm8Y= Received: by 10.236.174.3 with SMTP id w3mr13225195yhl.117.1320426251718; Fri, 04 Nov 2011 10:04:11 -0700 (PDT) Received: from localhost.localdomain ([71.46.235.243]) by mx.google.com with ESMTPS id d5sm16120500yhl.19.2011.11.04.10.04.10 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Nov 2011 10:04:11 -0700 (PDT) Sender: amit kachhap From: amit.kachhap@linaro.org To: linux-samsung-soc@vger.kernel.org Cc: linaro-dev@lists.linaro.org, linux-arm-kernel@lists.infradead.org, patches@linaro.org, kgene.kim@samsung.com, Amit Daniel Kachhap , Lorenzo Pieralisi Subject: [PATCH 3/4] ARM: exynos4: add L2 early resume code Date: Fri, 4 Nov 2011 13:03:47 -0400 Message-Id: <1320426228-21746-4-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1320426228-21746-1-git-send-email-amit.kachhap@linaro.org> References: <1320426228-21746-1-git-send-email-amit.kachhap@linaro.org> From: Amit Daniel Kachhap This patch adds code to save L2 register configuration at boot, and to resume L2 before MMU is enabled in suspend and cpuidle resume paths. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap --- arch/arm/mach-exynos4/cpu.c | 43 ++++++++++++++++++++++++++++++---------- arch/arm/mach-exynos4/sleep.S | 26 ++++++++++++++++++++++++ 2 files changed, 58 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index a348434..53c6cd3 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -11,6 +11,7 @@ #include #include +#include #include #include @@ -31,6 +32,7 @@ #include #include +#include unsigned int gic_bank_offset __read_mostly; @@ -254,20 +256,39 @@ core_initcall(exynos4_core_init); #ifdef CONFIG_CACHE_L2X0 static int __init exynos4_l2x0_cache_init(void) { - /* TAG, Data Latency Control: 2cycle */ - __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { - if (soc_is_exynos4210()) - __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - else if (soc_is_exynos4212() || soc_is_exynos4412()) - __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; + /* TAG, Data Latency Control: 2 cycles */ + l2x0_saved_regs.tag_latency = 0x110; + + if (soc_is_exynos4212() || soc_is_exynos4412()) + l2x0_saved_regs.data_latency = 0x120; + else + l2x0_saved_regs.data_latency = 0x110; + + l2x0_saved_regs.prefetch_ctrl = 0x30000007; + l2x0_saved_regs.pwr_ctrl = + (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN); - /* L2X0 Prefetch Control */ - __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); - /* L2X0 Power Control */ - __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, - S5P_VA_L2CC + L2X0_POWER_CTRL); + __raw_writel(l2x0_saved_regs.tag_latency, + S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + __raw_writel(l2x0_saved_regs.data_latency, + S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + + /* L2X0 Prefetch Control */ + __raw_writel(l2x0_saved_regs.prefetch_ctrl, + S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + + /* L2X0 Power Control */ + __raw_writel(l2x0_saved_regs.pwr_ctrl, + S5P_VA_L2CC + L2X0_POWER_CTRL); + + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); + clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); + } l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S index c19527b..3284213 100644 --- a/arch/arm/mach-exynos4/sleep.S +++ b/arch/arm/mach-exynos4/sleep.S @@ -27,6 +27,8 @@ */ #include +#include +#include .text @@ -47,7 +49,31 @@ * other way of restoring the stack pointer after sleep, and we * must not write to the code segment (code is read-only) */ + .align + .data ENTRY(s3c_cpu_resume) + adr r0, l2x0_regs_phys + ldr r0, [r0] + ldr r1, [r0, #L2X0_R_PHY_BASE] + ldr r2, [r1, #L2X0_CTRL] + tst r2, #0x1 + bne resume_l2on + ldr r2, [r0, #L2X0_R_AUX_CTRL] + str r2, [r1, #L2X0_AUX_CTRL] + ldr r2, [r0, #L2X0_R_TAG_LATENCY] + str r2, [r1, #L2X0_TAG_LATENCY_CTRL] + ldr r2, [r0, #L2X0_R_DATA_LATENCY] + str r2, [r1, #L2X0_DATA_LATENCY_CTRL] + ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] + str r2, [r1, #L2X0_PREFETCH_CTRL] + ldr r2, [r0, #L2X0_R_PWR_CTRL] + str r2, [r1, #L2X0_POWER_CTRL] + mov r2, #1 + str r2, [r1, #L2X0_CTRL] +resume_l2on: b cpu_resume ENDPROC(s3c_cpu_resume) + .globl l2x0_regs_phys +l2x0_regs_phys: + .long 0