From patchwork Fri Aug 19 13:09:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 3555 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D9AA323E54 for ; Fri, 19 Aug 2011 13:10:16 +0000 (UTC) Received: from mail-yi0-f52.google.com (mail-yi0-f52.google.com [209.85.218.52]) by fiordland.canonical.com (Postfix) with ESMTP id AA6BFA18071 for ; Fri, 19 Aug 2011 13:10:16 +0000 (UTC) Received: by yie13 with SMTP id 13so3139942yie.11 for ; Fri, 19 Aug 2011 06:10:16 -0700 (PDT) Received: by 10.151.6.13 with SMTP id j13mr2263673ybi.105.1313759416109; Fri, 19 Aug 2011 06:10:16 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.150.157.17 with SMTP id f17cs98125ybe; Fri, 19 Aug 2011 06:10:15 -0700 (PDT) Received: by 10.151.146.9 with SMTP id y9mr2299930ybn.99.1313759415678; Fri, 19 Aug 2011 06:10:15 -0700 (PDT) Received: from mail-iy0-f170.google.com (mail-iy0-f170.google.com [209.85.210.170]) by mx.google.com with ESMTPS id uo1si4445892icb.30.2011.08.19.06.10.14 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 19 Aug 2011 06:10:14 -0700 (PDT) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.170 as permitted sender) client-ip=209.85.210.170; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.170 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by iye16 with SMTP id 16so5571122iye.1 for ; Fri, 19 Aug 2011 06:10:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=Sm+MlQT2SlL43FHL6w1+w0muPHo/+c7gyTpusPyl4RM=; b=iBmwSy9o/He648n786hefthjGhbbBKscppnl0LIKT4W6YrDGgOIMieogpWifMf668Z 3PuiExhBCw4C4ZLRQQcZXxTX0ReAkJ8j8Nxi4ki0t5bl0fH4+Yjv2Z6fS6sfaURQZFWb pjhKYMK45u80Tm4/AeFFuh84oZA9ICdHjRbfQ= Received: by 10.142.188.7 with SMTP id l7mr1020444wff.385.1313759414145; Fri, 19 Aug 2011 06:10:14 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id l7sm2330298pbh.10.2011.08.19.06.10.11 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 19 Aug 2011 06:10:13 -0700 (PDT) Sender: amit kachhap From: Amit Daniel Kachhap To: linux-samsung-soc@vger.kernel.org Cc: linaro-dev@lists.linaro.org, linux-arm-kernel@lists.infradead.org, amit.kachhap@linaro.org, patches@linaro.org Subject: [RFC PATCH 2/4] ARM: EXYNOS4: Fix to work with origen boards. Date: Fri, 19 Aug 2011 18:39:58 +0530 Message-Id: <1313759400-31347-2-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1313759340-31319-1-git-send-email-amit.kachhap@linaro.org> References: <1313759340-31319-1-git-send-email-amit.kachhap@linaro.org> This adds a function to get the revision id. Signed-off-by: Jaecheol Lee Signed-off-by: Changhwan Youn --- arch/arm/mach-exynos4/cpu.c | 10 ++++++++++ arch/arm/plat-s5p/include/plat/exynos4.h | 1 + 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 2d8a40c..8b106b8 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -234,6 +234,16 @@ static int __init exynos4_l2x0_cache_init(void) early_initcall(exynos4_l2x0_cache_init); #endif +int exynos4_subrev(void) +{ + static int subrev = -1; + + if (unlikely(subrev < 0)) + subrev = readl(S5P_VA_CHIPID) & 0xf; + + return subrev; +} + int __init exynos4_init(void) { printk(KERN_INFO "EXYNOS4: Initializing architecture\n"); diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h index 907caab..d62f7f7 100644 --- a/arch/arm/plat-s5p/include/plat/exynos4.h +++ b/arch/arm/plat-s5p/include/plat/exynos4.h @@ -15,6 +15,7 @@ extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); extern void exynos4_register_clocks(void); extern void exynos4_setup_clocks(void); +extern int exynos4_subrev(void); #ifdef CONFIG_CPU_EXYNOS4210