From patchwork Fri Aug 19 13:09:57 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 3554 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2DD7323E54 for ; Fri, 19 Aug 2011 13:10:13 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id F1F4AA1837F for ; Fri, 19 Aug 2011 13:10:12 +0000 (UTC) Received: by ywo7 with SMTP id 7so3115302ywo.11 for ; Fri, 19 Aug 2011 06:10:12 -0700 (PDT) Received: by 10.150.170.13 with SMTP id s13mr2270814ybe.48.1313759412465; Fri, 19 Aug 2011 06:10:12 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.150.157.17 with SMTP id f17cs98123ybe; Fri, 19 Aug 2011 06:10:12 -0700 (PDT) Received: by 10.236.181.102 with SMTP id k66mr7395340yhm.49.1313759411997; Fri, 19 Aug 2011 06:10:11 -0700 (PDT) Received: from mail-pz0-f45.google.com (mail-pz0-f45.google.com [209.85.210.45]) by mx.google.com with ESMTPS id p6si7212907pbh.43.2011.08.19.06.10.11 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 19 Aug 2011 06:10:11 -0700 (PDT) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.45 as permitted sender) client-ip=209.85.210.45; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.45 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by pzk33 with SMTP id 33so6618694pzk.32 for ; Fri, 19 Aug 2011 06:10:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=Y1HxY8z9N3SZiDFEPCYtYCBQMFDXOii6tqaFIAY6F2c=; b=x6gMzbmf8p4JnUxoBpgRWz3zHcFYQ0WbWoO88WzI5alXZscNbgwTafWbka6vg55O7c xmVsukT9gOCg8Rrb1RA+RfbwqZvchGmrwlZcu5w/mI+5l/X4iKlM2LHHa+xUHPSYqUyE g6gUgPJHfYSc+i/4LPKRjSu0r/yM5hMcPt298= Received: by 10.142.44.13 with SMTP id r13mr448783wfr.286.1313759411371; Fri, 19 Aug 2011 06:10:11 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id l7sm2330298pbh.10.2011.08.19.06.10.08 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 19 Aug 2011 06:10:10 -0700 (PDT) Sender: amit kachhap From: Amit Daniel Kachhap To: linux-samsung-soc@vger.kernel.org Cc: linaro-dev@lists.linaro.org, linux-arm-kernel@lists.infradead.org, amit.kachhap@linaro.org, patches@linaro.org Subject: [RFC PATCH 1/4] ARM: kernel: Small fixes in save/restore common code. Date: Fri, 19 Aug 2011 18:39:57 +0530 Message-Id: <1313759400-31347-1-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1313759340-31319-1-git-send-email-amit.kachhap@linaro.org> References: <1313759340-31319-1-git-send-email-amit.kachhap@linaro.org> These changes are necessary to make the retention cpuidle state work. This adds support for saving more L2 registers. Signed-off-by: Amit Daniel Kachhap --- arch/arm/common/gic.c | 1 - arch/arm/kernel/sr_helpers.h | 2 +- arch/arm/mm/cache-l2x0.c | 10 +++++++++- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index d845b75..124e122 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -385,7 +385,6 @@ static void gic_dist_save(unsigned int gic_nr) gic_data[gic_nr].saved_spi_enable[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); - writel_relaxed(0, dist_base + GIC_DIST_CTRL); } /* diff --git a/arch/arm/kernel/sr_helpers.h b/arch/arm/kernel/sr_helpers.h index 1ae3a9a..5a30461 100644 --- a/arch/arm/kernel/sr_helpers.h +++ b/arch/arm/kernel/sr_helpers.h @@ -44,7 +44,7 @@ static inline void exit_coherency(void) "mcr p15, 0, %0, c1, c0, 1\n" : "=&r" (v) : "Ir" (0x40) - : ); + : "cc"); } #else static inline void exit_coherency(void) { } diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 4c99d41..f23696b 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -285,7 +285,11 @@ static void l2x0_save_context(void *data, bool dormant, unsigned long end) *l2x0_regs = readl_relaxed(l2x0_base + L2X0_TAG_LATENCY_CTRL); l2x0_regs++; *l2x0_regs = readl_relaxed(l2x0_base + L2X0_DATA_LATENCY_CTRL); - + l2x0_regs++; + *l2x0_regs = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); + l2x0_regs++; + *l2x0_regs = readl_relaxed(l2x0_base + L2X0_POWER_CTRL); + dormant = 0; if (!dormant) { /* clean entire L2 before disabling it*/ writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY); @@ -325,6 +329,10 @@ static void l2x0_restore_context(void *data, bool dormant) writel_relaxed(*l2x0_regs, l2x0_base + L2X0_TAG_LATENCY_CTRL); l2x0_regs++; writel_relaxed(*l2x0_regs, l2x0_base + L2X0_DATA_LATENCY_CTRL); + l2x0_regs++; + writel_relaxed(*l2x0_regs, l2x0_base + L2X0_PREFETCH_CTRL); + l2x0_regs++; + writel_relaxed(*l2x0_regs, l2x0_base + L2X0_POWER_CTRL); /* * If L2 is retained do not invalidate */