From patchwork Tue May 10 06:13:50 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inderpal Singh X-Patchwork-Id: 1426 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:51:53 -0000 Delivered-To: patches@linaro.org Received: by 10.224.61.3 with SMTP id r3cs7356qah; Mon, 9 May 2011 23:14:38 -0700 (PDT) Received: by 10.42.239.6 with SMTP id ku6mr6808573icb.189.1305008077804; Mon, 09 May 2011 23:14:37 -0700 (PDT) Received: from mail-pv0-f178.google.com (mail-pv0-f178.google.com [74.125.83.178]) by mx.google.com with ESMTPS id t14si19010670ibm.34.2011.05.09.23.14.36 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 09 May 2011 23:14:36 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.83.178 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) client-ip=74.125.83.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.83.178 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) smtp.mail=inderpal.singh@linaro.org Received: by pvg7 with SMTP id 7so3647362pvg.37 for ; Mon, 09 May 2011 23:14:35 -0700 (PDT) Received: by 10.142.188.1 with SMTP id l1mr4113112wff.346.1305008075581; Mon, 09 May 2011 23:14:35 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id n7sm9088858wfl.23.2011.05.09.23.14.31 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 09 May 2011 23:14:34 -0700 (PDT) From: Inderpal Singh To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: kgene.kim@samsung.com, samsung@lists.linaro.org, patches@linaro.org, jc.lee@samsung.com, Inderpal Singh Subject: [PATCH] ARM: EXYNOS4: Suspend to RAM fix Date: Tue, 10 May 2011 11:43:50 +0530 Message-Id: <1305008030-31983-1-git-send-email-inderpal.s@samsung.com> X-Mailer: git-send-email 1.7.1 This patch caters to the case when there is no wake up source. The system should abort the suspend and resume properly. 1. It implements the pm_suspend function to save the core registers so that they can be restored in pm_resume function. Earlier these resgisters were getting saved in pm_prepare, but pm_prepare never gets invoked when there is no wake up source enabled and restoration used to hang while resuming. 2. As per the L2 cache controller spec, the cache controller registers should not be modified if cache is already enabled. Hence have made restoration of cache controller registers conditional based on whether it is already enabled or not. Signed-off-by: Inderpal Singh Signed-off-by: Jaecheol Lee --- arch/arm/mach-exynos4/pm.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index 10d917d..af4794b 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c @@ -323,8 +323,9 @@ static void exynos4_pm_prepare(void) { u32 tmp; - s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); +#ifdef CONFIG_CACHE_L2X0 s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); +#endif tmp = __raw_readl(S5P_INFORM1); @@ -389,6 +390,10 @@ static int exynos4_pm_resume(struct sys_device *dev) exynos4_scu_enable(S5P_VA_SCU); #ifdef CONFIG_CACHE_L2X0 + /* Restore the cache controller registers only if it is not enabled already*/ + if((__raw_readl(S5P_VA_L2CC + L2X0_CTRL)&1)) + return 0; + s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); outer_inv_all(); /* enable L2X0*/ @@ -398,9 +403,16 @@ static int exynos4_pm_resume(struct sys_device *dev) return 0; } +static int exynos4_pm_suspend(struct sys_device *dev,pm_message_t state) +{ + s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); + return 0; +} + static struct sysdev_driver exynos4_pm_driver = { .add = exynos4_pm_add, .resume = exynos4_pm_resume, + .suspend = exynos4_pm_suspend, }; static __init int exynos4_pm_drvinit(void)