[v2,0/3] add CPUCL0 clock support for exynosauto v920 SoC

Message ID	20250423044153.1288077-1-shin.son@samsung.com
Headers	show Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 318CB26562B for <linux-samsung-soc@vger.kernel.org>; Wed, 23 Apr 2025 04:42:03 +0000 (UTC) From: Shin Son <shin.son@samsung.com> To: Krzysztof Kozlowski <krzk@kernel.org>, Sylwester Nawrocki <s.nawrocki@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Alim Akhtar <alim.akhtar@samsung.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Sunyeal Hong <sunyeal.hong@samsung.com> Cc: Shin Son <shin.son@samsung.com>, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/3] add CPUCL0 clock support for exynosauto v920 SoC Date: Wed, 23 Apr 2025 13:41:50 +0900 Message-ID: <20250423044153.1288077-1-shin.son@samsung.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y References: <CGME20250423044159epcas2p2a064b6cd52806f765f830240adaf69a5@epcas2p2.samsung.com>
Series	add CPUCL0 clock support for exynosauto v920 SoC \| expand [v2,0/3] add CPUCL0 clock support for exynosauto v920 SoC [v2,1/3] dt-bindings: clock: exynosautov920: add cpucl0 clock definitions [v2,2/3] clk: samsung: exynosautov920: add cpucl0 clock support [v2,3/3] arm64: dts: exynosautov920: add cpucl0 clock DT nodes

Message ID

20250423044153.1288077-1-shin.son@samsung.com

Headers

From: Shin Son <shin.son@samsung.com>
To: Krzysztof Kozlowski <krzk@kernel.org>, Sylwester Nawrocki
	<s.nawrocki@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Alim Akhtar
	<alim.akhtar@samsung.com>, Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, Conor Dooley
	<conor+dt@kernel.org>, Sunyeal Hong <sunyeal.hong@samsung.com>
Cc: Shin Son <shin.son@samsung.com>, linux-samsung-soc@vger.kernel.org,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 0/3] add CPUCL0 clock support for exynosauto v920 SoC
Date: Wed, 23 Apr 2025 13:41:50 +0900
Message-ID: <20250423044153.1288077-1-shin.son@samsung.com>
Precedence: bulk
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain; charset="utf-8"
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References: 
 <CGME20250423044159epcas2p2a064b6cd52806f765f830240adaf69a5@epcas2p2.samsung.com>

Series

add CPUCL0 clock support for exynosauto v920 SoC | expand

Message

손신 April 23, 2025, 4:41 a.m. UTC

This patchset adds the CMU_CPUCL0 block to support exynosauto v920 SoC

Changes in v2:
- Add a brief description of the hardware
- Explain why CLK_OF_DECLARE is used
- Convert uppercase hex value to lowercase
- Aligned previously misaligned lines

Shin Son (3):
  dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
  clk: samsung: exynosautov920: add cpucl0 clock support
  arm64: dts: exynosautov920: add cpucl0 clock DT nodes

 .../clock/samsung,exynosautov920-clock.yaml   |  25 ++++
 .../arm64/boot/dts/exynos/exynosautov920.dtsi |  15 ++
 drivers/clk/samsung/clk-exynosautov920.c      | 130 ++++++++++++++++++
 .../clock/samsung,exynosautov920.h            |  19 +++
 4 files changed, 189 insertions(+)

Comments

Krzysztof Kozlowski April 27, 2025, 7:25 p.m. UTC | #1

On Wed, 23 Apr 2025 13:41:53 +0900, Shin Son wrote:
> Add cmu_cpucl0 clocks for switch, cluster, and dbg domains respectively.
> 
> 

Applied, thanks!

[3/3] arm64: dts: exynosautov920: add cpucl0 clock DT nodes
      https://git.kernel.org/krzk/linux/c/2a4067c89e4137c477ca6f367e65ace0f2132922

Best regards,