Message ID | 20241127-gs101-phy-lanes-orientation-dts-v1-0-5222d8508b71@linaro.org |
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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b339612sm693762966b.84.2024.11.27.03.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Nov 2024 03:01:39 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org> Subject: [PATCH 0/6] Google Pixel 6 (oriole): TCPCI enablement & USB updates Date: Wed, 27 Nov 2024 11:01:38 +0000 Message-Id: <20241127-gs101-phy-lanes-orientation-dts-v1-0-5222d8508b71@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: <linux-samsung-soc.vger.kernel.org> List-Subscribe: <mailto:linux-samsung-soc+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-samsung-soc+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIABL8RmcC/x2NQQqDQAwAvyI5N2CCRepXpIewphooq2yWUhH/b vA4h5k5wLWYOgzNAUV/5rbmAHo0kBbJs6JNwcAtd0Tc4+zUEm7Ljl/J6riGnqvU8HCqji9J2nf CiZ8JorIV/dj/Pozv87wAXVvef3EAAAA= To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Jagan Sridharan <badhri@google.com>, Alim Akhtar <alim.akhtar@samsung.com> Cc: Peter Griffin <peter.griffin@linaro.org>, Tudor Ambarus <tudor.ambarus@linaro.org>, Sam Protsenko <semen.protsenko@linaro.org>, Will McVicker <willmcvicker@google.com>, Roy Luo <royluo@google.com>, kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, =?utf-8?q?A?= =?utf-8?q?ndr=C3=A9_Draszik?= <andre.draszik@linaro.org> X-Mailer: b4 0.13.0 |
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Google Pixel 6 (oriole): TCPCI enablement & USB updates
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Hi, This series adds and enables the Maxim MAX77759 TCPCI for Google Pixel 6 (Oriole). It relies on the bindings update proposed as part of https://lore.kernel.org/r/20241127-gs101-phy-lanes-orientation-phy-v1-0-1b7fce24960b@linaro.org With these patches, we allow the usb phy to detect usb cable orientation, and we make it possible for the USB DWC3 core to enter runtime suspend upon cable disconnect. Signed-off-by: André Draszik <andre.draszik@linaro.org> --- André Draszik (6): arm64: defconfig: enable Maxim TCPCI driver dt-bindings: usb: max33359: add max77759 flavor arm64: dts: exynos: gs101: phy region for exynos5-usbdrd is larger arm64: dts: exynos: gs101: enable snps,dis_rxdet_inp3_quirk for DWC3 arm64: dts: exynos: gs101-oriole: enable Maxim max77759 TCPCi arm64: dts: exynos: gs101-oriole: add pd-disable and typec-power-opmode .../devicetree/bindings/usb/maxim,max33359.yaml | 8 +- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 104 +++++++++++++++++++++ arch/arm64/boot/dts/exynos/google/gs101.dtsi | 3 +- arch/arm64/configs/defconfig | 1 + 4 files changed, 113 insertions(+), 3 deletions(-) --- base-commit: ed9a4ad6e5bd3a443e81446476718abebee47e82 change-id: 20241127-gs101-phy-lanes-orientation-dts-9ace74a2c25c Best regards,