Message ID | 20240429-hsi0-gs101-v3-0-f233be0a2455@linaro.org |
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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id dk21-20020a170907941500b00a55aee4bf74sm9976074ejc.79.2024.04.29.06.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 06:02:29 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org> Subject: [PATCH v3 0/3] HSI2 support for Google Tensor gs101 Date: Mon, 29 Apr 2024 14:02:16 +0100 Message-Id: <20240429-hsi0-gs101-v3-0-f233be0a2455@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: <linux-samsung-soc.vger.kernel.org> List-Subscribe: <mailto:linux-samsung-soc+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-samsung-soc+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAFiaL2YC/23MQQqDMBCF4avIrJuSTNRIV71H6WI0UQeKKUkJL eLdm7iq0OV78P0rRBfYRbhUKwSXOLJf8tCnCoaZlskJtnkDSqxljVrMkaWYopJKEBnT6Vb1IxF k8Axu5Pceu93znjm+fPjs7aTK+zeTlJACB21t38jBoLw+eKHgzz5MUDoJf217sFisaoylrm+10 we7bdsX8bKcUOEAAAA= To: Peter Griffin <peter.griffin@linaro.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Alim Akhtar <alim.akhtar@samsung.com>, Krzysztof Kozlowski <krzk@kernel.org>, Sylwester Nawrocki <s.nawrocki@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com> Cc: Tudor Ambarus <tudor.ambarus@linaro.org>, Will McVicker <willmcvicker@google.com>, kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org> X-Mailer: b4 0.12.4 |
Series | HSI2 support for Google Tensor gs101 | expand |
On Mon, 29 Apr 2024 14:02:19 +0100, André Draszik wrote: > CMU_HSI2 is the clock management unit used for the hsi2 block. > HSI stands for High Speed Interface and as such it generates > clocks for PCIe, UFS and MMC card. > > This patch adds support for the muxes, dividers, and gates in > cmu_hsi2. > > [...] Applied, thanks! [3/3] clk: samsung: gs101: add support for cmu_hsi2 https://git.kernel.org/krzk/linux/c/093c290084a494844f1650e70755b8912292ee14 Best regards,
This patch series enables the HSI2 (high speed interfaces) for gs101: - HSI2 feeds PCIe and UFS The parts added here have been verified to work OK without the clk_ignore_unused kernel command line option. Signed-off-by: André Draszik <andre.draszik@linaro.org> --- Changes in v3: - Drop HSI0-related changes as already applied - s/ufs_embd/ufs and s/mmc_card/mmc (Tudor, Krzysztof) - collect tags - drop my own R-b tag, due to SoB - Link to v2: https://lore.kernel.org/r/20240426-hsi0-gs101-v2-0-2157da8b63e3@linaro.org Changes in v2: - My v1 just contained HSI0, but due due to changing similar areas in the code, I've also added Peter's HSI2 clock patches from https://lore.kernel.org/all/20240423205006.1785138-1-peter.griffin@linaro.org to this series so as to preempt any merge conflicts. Namely: * hsi2 bindings * hsi2 DT * hsi2 cmu clock driver - drop patch 'dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit' as already applied - cometic updates to patch 4: 'clk: samsung: gs101: add support for cmu_hsi0' (macro name, a whitespace, subject line) - Link to v1: https://lore.kernel.org/r/20240423-hsi0-gs101-v1-0-2c3ddb50c720@linaro.org --- Peter Griffin (3): dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller clk: samsung: gs101: add support for cmu_hsi2 .../bindings/clock/google,gs101-clock.yaml | 26 ++ arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 + drivers/clk/samsung/clk-gs101.c | 507 +++++++++++++++++++++ include/dt-bindings/clock/google,gs101.h | 62 +++ 4 files changed, 607 insertions(+) --- base-commit: b0a2c79c6f3590b74742cbbc76687014d47972d8 change-id: 20240423-hsi0-gs101-aa778361bfaa Best regards,