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[0/6] fsys0/1 clock support for Exynos Auto v9 SoC

Message ID 20220727060146.9228-1-chanho61.park@samsung.com
Headers show
Series fsys0/1 clock support for Exynos Auto v9 SoC | expand

Message

Chanho Park July 27, 2022, 6:01 a.m. UTC 
CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2
Lanes. Similarly, CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1,
2 x USB 2.0) and mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also
supported as a PLL source clock provider.

Chanho Park (6):
  dt-bindings: clk: exynosautov9: add fys0 clock definitions
  dt-bindings: clock: exynosautov9: add fsys1 clock definitions
  dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
  arm64: dts: exynosautov9: add fsys0/1 clock DT nodes
  clk: samsung: exynosautov9: add fsys0 clock support
  clk: samsung: exynosautov9: add fsys1 clock support

 .../clock/samsung,exynosautov9-clock.yaml     |  44 +++
 arch/arm64/boot/dts/exynos/exynosautov9.dtsi  |  28 ++
 drivers/clk/samsung/clk-exynosautov9.c        | 372 ++++++++++++++++++
 .../dt-bindings/clock/samsung,exynosautov9.h  |  68 ++++
 4 files changed, 512 insertions(+)