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[209.132.180.67]) by mx.google.com with ESMTP id z77si12352839pfk.411.2017.03.20.05.47.43; Mon, 20 Mar 2017 05:47:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753568AbdCTMrk (ORCPT + 13 others); Mon, 20 Mar 2017 08:47:40 -0400 Received: from mail-pg0-f52.google.com ([74.125.83.52]:36239 "EHLO mail-pg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753292AbdCTJca (ORCPT ); Mon, 20 Mar 2017 05:32:30 -0400 Received: by mail-pg0-f52.google.com with SMTP id g2so74180035pge.3 for ; Mon, 20 Mar 2017 02:32:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=rccACnoRe9et99W6tONd3fZLSnYmGJ3LRnMFYyfQvTk=; b=IEOW3o8GVX1+O7cjihZ2CnmKMfbeLh2JPOmO7SmfzAdypAKerDciA3N+Qq0IQd/1gE OfglTHAGS72XzKTpw1QxaBAGO72Zc9t+QgwW/nex/8uwqJdUalbjJodDLJCUILxUjKqk aqYDgVNT1SCO5qvm4w6jb9WzcElNNe/WCQChw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=rccACnoRe9et99W6tONd3fZLSnYmGJ3LRnMFYyfQvTk=; b=WH/c4rjnvVmzu54dhjQgVu8LiajAYJDc+au4CqxbRy77AWBE9N0lPrh1BszpIKNf7l 2alAwC76Pme7+7zsUAbBr7HH2a3zQT0ixTjg82xk5JZodyhvSE5vZ4Ta7VOUoj02Sexm BDzGtAFb97s4VlYNoM9vcJiBDI6lYub565klQF4eBhtKB2Kfa/XtxVBFIPv4EP9n7+CJ /KQAQ7Szm/aD+c0uOjNqUBIBaanFw08J+BVoR2eS/txjwrdet1YynB+76tZZPhSz5uxn X6zooF/4qalMNNIUk30gcRLZr1icS0553mz34WhbOrbVYwLqxoGRFT2ib8KOjW2MPxGe 8UfQ== X-Gm-Message-State: AFeK/H29pMQJKSs5+rrwqefpmj1T2krLzq7BNZgNqUMF35Uo2S3JiA5X/GQnBQBDSU/nF/i1 X-Received: by 10.99.123.15 with SMTP id w15mr12398741pgc.125.1490002348716; Mon, 20 Mar 2017 02:32:28 -0700 (PDT) Received: from localhost ([122.171.239.200]) by smtp.gmail.com with ESMTPSA id e67sm3625993pfa.87.2017.03.20.02.32.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Mar 2017 02:32:28 -0700 (PDT) From: Viresh Kumar To: Rafael Wysocki , ulf.hansson@linaro.org, Kevin Hilman , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linaro-kernel@lists.linaro.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Vincent Guittot , robh+dt@kernel.org, lina.iyer@linaro.org, rnayak@codeaurora.org, Viresh Kumar , devicetree@vger.kernel.org Subject: [PATCH V4 1/9] PM / OPP: Allow OPP table to be used for power-domains Date: Mon, 20 Mar 2017 15:02:13 +0530 Message-Id: X-Mailer: git-send-email 2.12.0.432.g71c3a4f4ba37 In-Reply-To: References: In-Reply-To: References: Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Power-domains need to express their active states in DT and what's better than OPP table for that. This patch allows power-domains to reuse OPP tables to express their active states. The "opp-hz" property isn't a required property anymore as power-domains may not always use them. Add a new property "domain-performance-state", which will contain positive integer values to represent performance levels of the power-domains as described in this patch. Signed-off-by: Viresh Kumar --- Documentation/devicetree/bindings/opp/opp.txt | 73 ++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 2 deletions(-) -- 2.12.0.432.g71c3a4f4ba37 diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt index 63725498bd20..d0b95c9e1011 100644 --- a/Documentation/devicetree/bindings/opp/opp.txt +++ b/Documentation/devicetree/bindings/opp/opp.txt @@ -76,10 +76,9 @@ This describes the OPPs belonging to a device. This node can have following This defines voltage-current-frequency combinations along with other related properties. -Required properties: +Optional properties: - opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. -Optional properties: - opp-microvolt: voltage in micro Volts. A single regulator's voltage is specified with an array of size one or three. @@ -154,6 +153,19 @@ properties. - status: Marks the node enabled/disabled. +- domain-performance-state: A positive integer value representing the minimum + power-domain performance level required by the device for the OPP node. The + integer value '0' represents the lowest performance level and the higher + values represent higher performance levels. When present in the OPP table of a + power-domain, it represents the performance level of the domain. When present + in the OPP table of a normal device, it represents the performance level of + the parent power-domain. The OPP table can contain the + "domain-performance-state" property, only if the device node contains the + "power-domains" or "#power-domain-cells" property. The OPP nodes aren't + allowed to contain the "domain-performance-state" property partially, i.e. + Either all OPP nodes in the OPP table have the "domain-performance-state" + property or none of them have it. + Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. / { @@ -528,3 +540,60 @@ Example 5: opp-supported-hw }; }; }; + +Example 7: domain-Performance-state: +(example: For 1GHz require domain state 1 and for 1.1 & 1.2 GHz require state 2) + +/ { + domain_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@1 { + domain-performance-state = <1>; + opp-microvolt = <975000 970000 985000>; + }; + opp@2 { + domain-performance-state = <2>; + opp-microvolt = <1075000 1000000 1085000>; + }; + }; + + foo_domain: power-controller@12340000 { + compatible = "foo,power-controller"; + reg = <0x12340000 0x1000>; + #power-domain-cells = <0>; + operating-points-v2 = <&domain_opp_table>; + } + + cpu0_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + domain-performance-state = <1>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + domain-performance-state = <2>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + domain-performance-state = <2>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + power-domains = <&foo_domain>; + }; + }; +};