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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00001CDE.mail.protection.outlook.com (10.167.242.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7587.21 via Frontend Transport; Mon, 13 May 2024 02:08:16 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Sun, 12 May 2024 21:08:13 -0500 From: Perry Yuan To: , , , CC: , , , , , , Subject: [PATCH v2 09/10] cpufreq: amd-pstate: implement heterogeneous core topology for highest performance initialization Date: Mon, 13 May 2024 10:07:27 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CDE:EE_|CY5PR12MB6323:EE_ X-MS-Office365-Filtering-Correlation-Id: 71010524-b9ee-4708-d3eb-08dc72f18d63 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(376005)(36860700004)(1800799015)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 May 2024 02:08:16.3332 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71010524-b9ee-4708-d3eb-08dc72f18d63 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6323 Introduces an optimization to the AMD-Pstate driver by implementing a heterogeneous core topology for the initialization of the highest performance value while driver loading. There are two type cores designed including performance core and Efficiency Core. Each core type has different highest performance and frequency values configured by the platform. The `amd_pstate` driver needs to identify the type of core to correctly set an appropriate highest perf value. X86_FEATURE_HETERO_CORE_TOPOLOGY is used to identify whether the processor support heterogeneous core type by reading CPUID leaf Fn_0x80000026_EAX and bit 30. if the bit is set as one, then amd_pstate driver will check EBX 30:28 bits to get the core type. Link: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf PDF p274 Signed-off-by: Perry Yuan --- arch/x86/include/asm/processor.h | 2 + arch/x86/kernel/cpu/amd.c | 19 +++++++++ drivers/cpufreq/amd-pstate.c | 66 ++++++++++++++++++++------------ include/linux/amd-pstate.h | 8 ++++ 4 files changed, 71 insertions(+), 24 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 78e51b0d6433..04d30dd35d0a 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -682,10 +682,12 @@ static inline u32 per_cpu_l2c_id(unsigned int cpu) extern u32 amd_get_highest_perf(void); extern void amd_clear_divider(void); extern void amd_check_microcode(void); +extern int amd_get_this_core_type(void); #else static inline u32 amd_get_highest_perf(void) { return 0; } static inline void amd_clear_divider(void) { } static inline void amd_check_microcode(void) { } +static inline int amd_get_this_core_type(void) { return -1; } #endif extern unsigned long arch_align_stack(unsigned long sp); diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 307302af0aee..67966bdcde65 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1219,3 +1219,22 @@ void noinstr amd_clear_divider(void) :: "a" (0), "d" (0), "r" (1)); } EXPORT_SYMBOL_GPL(amd_clear_divider); + +#define X86_CPU_TYPE_ID_SHIFT 28 + +/** + * amd_get_this_core_type - Get the type of this heterogeneous CPU + * + * Returns the CPU type [31:28] (i.e., performance or efficient) of + * a CPU in the processor. + * If the processor has no core type support, returns -1. + */ + +int amd_get_this_core_type(void) +{ + if (!cpu_feature_enabled(X86_FEATURE_HETERO_CORE_TOPOLOGY)) + return -1; + + return cpuid_ebx(0x80000026) >> X86_CPU_TYPE_ID_SHIFT; +} +EXPORT_SYMBOL_GPL(amd_get_this_core_type); diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 8b8cae1b678d..dce901a403c9 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -50,8 +50,9 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 -#define CPPC_HIGHEST_PERF_PERFORMANCE 196 -#define CPPC_HIGHEST_PERF_DEFAULT 166 +#define CPPC_HIGHEST_PERF_EFFICIENT 132 +#define CPPC_HIGHEST_PERF_PERFORMANCE 196 +#define CPPC_HIGHEST_PERF_DEFAULT 166 /* * TODO: We need more time to fine tune processors with shared memory solution @@ -327,19 +328,47 @@ static inline int amd_pstate_enable(bool enable) return static_call(amd_pstate_enable)(enable); } +static void get_this_core_type(void *data) +{ + int *cpu_type = data; + + *cpu_type = amd_get_this_core_type(); +} + +static int amd_pstate_get_cpu_type(int cpu) +{ + int cpu_type = 0; + + smp_call_function_single(cpu, get_this_core_type, &cpu_type, 1); + + return cpu_type; +} + static u32 amd_pstate_highest_perf_set(struct amd_cpudata *cpudata) { - struct cpuinfo_x86 *c = &cpu_data(0); + u32 highest_perf; + int core_type; - /* - * For AMD CPUs with Family ID 19H and Model ID range 0x70 to 0x7f, - * the highest performance level is set to 196. - * https://bugzilla.kernel.org/show_bug.cgi?id=218759 - */ - if (c->x86 == 0x19 && (c->x86_model >= 0x70 && c->x86_model <= 0x7f)) - return CPPC_HIGHEST_PERF_PERFORMANCE; + core_type = amd_pstate_get_cpu_type(cpudata->cpu); + pr_debug("core_type %d found\n", core_type); - return CPPC_HIGHEST_PERF_DEFAULT; + switch (core_type) { + case CPU_CORE_TYPE_NO_HETERO_SUP: + highest_perf = CPPC_HIGHEST_PERF_DEFAULT; + break; + case CPU_CORE_TYPE_PERFORMANCE: + highest_perf = CPPC_HIGHEST_PERF_PERFORMANCE; + break; + case CPU_CORE_TYPE_EFFICIENCY: + highest_perf = CPPC_HIGHEST_PERF_EFFICIENT; + break; + default: + highest_perf = CPPC_HIGHEST_PERF_DEFAULT; + WARN_ONCE(true, "WARNING: Undefined core type found"); + break; + } + + return highest_perf; } static int pstate_init_perf(struct amd_cpudata *cpudata) @@ -352,15 +381,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) if (ret) return ret; - /* For platforms that do not support the preferred core feature, the - * highest_pef may be configured with 166 or 255, to avoid max frequency - * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as - * the default max perf. - */ - if (cpudata->hw_prefcore) - highest_perf = amd_pstate_highest_perf_set(cpudata); - else - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); + highest_perf = amd_pstate_highest_perf_set(cpudata); WRITE_ONCE(cpudata->highest_perf, highest_perf); WRITE_ONCE(cpudata->max_limit_perf, highest_perf); @@ -381,10 +402,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata) if (ret) return ret; - if (cpudata->hw_prefcore) - highest_perf = amd_pstate_highest_perf_set(cpudata); - else - highest_perf = cppc_perf.highest_perf; + highest_perf = amd_pstate_highest_perf_set(cpudata); WRITE_ONCE(cpudata->highest_perf, highest_perf); WRITE_ONCE(cpudata->max_limit_perf, highest_perf); diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index d58fc022ec46..869d916003f1 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -134,4 +134,12 @@ struct quirk_entry { u32 lowest_freq; }; +/* defined by CPUID_Fn80000026_EBX BIT [31:28] */ +enum amd_core_type { + CPU_CORE_TYPE_NO_HETERO_SUP = -1, + CPU_CORE_TYPE_PERFORMANCE = 0, + CPU_CORE_TYPE_EFFICIENCY = 1, + CPU_CORE_TYPE_UNDEFINED = 2, +}; + #endif /* _LINUX_AMD_PSTATE_H */