From patchwork Thu Feb 27 15:52:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 869173 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EF0426E153; Thu, 27 Feb 2025 15:53:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740671592; cv=none; b=NZoeyCenaYeGBqR2TLF5xhTCVULYOOIz226IGoOTcmnCy/pgJU0GpsYEYfsMoT+TfDr6IqWjoW/aqFjDFDglzBoi+/EWt4slaXl1QGRFIlyWLkcnkK+IIQ2kYFF9hk57m8cl/NKxAiJkvu2bS4RjG7y/8GMG4OhofMoTODXwuBw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740671592; c=relaxed/simple; bh=9bsGD1HtLiE5n6V0YC+e3jk1OxXU7Mp7V0z9UDJ1XPc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fG0sOajLYNRExC07uQ3NTmiQbGrrF/Lwdnu/EPI0HHfJ3uk8OYsQLUkDOrqztBnlHfAJpP9by50G/HPLKB1wMjai5nB2PmXpdRV4PvYGbXoAhB5dYBMdkD7B+2xpXVC65ch/kWQWWJzdgRIISe+VFi0pLrJxPsQYNH8ePfhizho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=enrlKNEl; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="enrlKNEl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1740671590; x=1772207590; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9bsGD1HtLiE5n6V0YC+e3jk1OxXU7Mp7V0z9UDJ1XPc=; b=enrlKNEldQNlBNs05fM07yafEd3sHozyYzw1HjVH3R4YA81nu9XhLSC6 EYTJwXFnsSPFdelnE3Cnlq5AlK1fx5nvrTwN+/tqbowuYLVgqAq/zp2Yy SUTZobCRh9cj//Xm4mjGjiXM1WBR1Ho7KwRKGWAwOFNz0lwJ+I3C+TeCb GYLRugUZ+YYsbaYPaUxFAb68SDy4ngPLvQh4KWefUf68SvIzjiQUjNx2i ZlByuXV8howr8k5UKYusynUvbSF8JikBoC3vrmrPX1RJJVo3I6Dv+0jGU hjHUVHaD0RpFEkhSEFGu+vtbWcd2AL6/f204pjP699FlZZ33uB69Navzp g==; X-CSE-ConnectionGUID: xBkIAngZQVSwQhIMCQbtUA== X-CSE-MsgGUID: UmESS6IjRrOgI0xd1tUzAg== X-IronPort-AV: E=Sophos;i="6.13,320,1732604400"; d="scan'208";a="38638180" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 27 Feb 2025 08:52:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 27 Feb 2025 08:52:46 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 27 Feb 2025 08:52:46 -0700 From: To: , , , , , , , , CC: , , , , , , "Ryan Wanner" Subject: [PATCH v3 15/21] ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoC Date: Thu, 27 Feb 2025 08:52:02 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add Reset Controller support to SAMA7D65 SoC. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index c10cc3558efd..5165259fb926 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -102,6 +102,13 @@ pmc: clock-controller@e0018000 { clock-names = "td_slck", "md_slck", "main_xtal"; }; + reset_controller: reset-controller@e001d100 { + compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; + reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + clk32k: clock-controller@e001d500 { compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d500 0x4>;