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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D9.mail.protection.outlook.com (10.167.241.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Tue, 30 Jan 2024 03:19:11 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Mon, 29 Jan 2024 21:19:03 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH 2/8] tools/power x86_energy_perf_policy: enable AMD pstate EPP profile switching on MSR based system Date: Tue, 30 Jan 2024 11:18:30 +0800 Message-ID: <8572a009206244f4caae5a4c9db3c475cfacc289.1706583551.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D9:EE_|BL1PR12MB5351:EE_ X-MS-Office365-Filtering-Correlation-Id: 86626450-f4ee-491e-bc78-08dc21423a8e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2024 03:19:11.2821 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86626450-f4ee-491e-bc78-08dc21423a8e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5351 From: Perry Yuan x86_energy_perf_policy adds AMD EPP profiles switch support,the EPP driver also has four EPP profiles implemented under power firmware autonomous mode. (performance, balance-performance, balance-power, power) User can choose the new profile to use with this utility support while `amd_pstate_epp` driver instance loaded for the MSR support systems. for example: $ sudo x86_energy_perf_policy -d --hwp-epp balance-performance cpu0: old: HWP_REQ: min 13 max 166 des 0 epp 128 window 0x9 (9*10^0us) use_pkg 0 cpu0: HWP_CAP: low 13 eff 157 guar 0 high 231 cpu0: new: HWP_REQ: min 13 max 166 des 0 epp 128 window 0x9 (9*10^0us) use_pkg 0 cpu1: old: HWP_REQ: min 13 max 166 des 0 epp 128 window 0x9 (9*10^0us) use_pkg 0 cpu1: HWP_CAP: low 13 eff 157 guar 0 high 236 cpu1: new: HWP_REQ: min 13 max 166 des 0 epp 128 window 0x9 (9*10^0us) use_pkg 0 cpu2: old: HWP_REQ: min 13 max 166 des 0 epp 128 window 0x9 (9*10^0us) use_pkg 0 cpu2: HWP_CAP: low 13 eff 157 guar 0 high 211 cpu2: new: HWP_REQ: min 13 max 166 des 0 epp 128 window 0x9 (9*10^0us) use_pkg 0 cpu3: old: HWP_REQ: min 13 max 166 des 0 epp 128 window 0x9 (9*10^0us) use_pkg 0 cpu3: HWP_CAP: low 13 eff 157 guar 0 high 206 cpu3: new: HWP_REQ: min 13 max 166 des 0 epp 128 window 0x9 (9*10^0us) use_pkg 0 Signed-off-by: Perry Yuan --- .../x86_energy_perf_policy.c | 69 +++++++++++++++---- 1 file changed, 54 insertions(+), 15 deletions(-) diff --git a/tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c b/tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c index 5daf1c2bb601..da9087873915 100644 --- a/tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c +++ b/tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c @@ -902,14 +902,23 @@ void write_hwp_request(int cpu, struct msr_hwp_request *hwp_req, unsigned int ms hwp_req->hwp_desired, hwp_req->hwp_epp, hwp_req->hwp_window, hwp_req->hwp_use_pkg); - msr |= HWP_MIN_PERF(ratio_2_msr_perf(hwp_req->hwp_min)); - msr |= HWP_MAX_PERF(ratio_2_msr_perf(hwp_req->hwp_max)); - msr |= HWP_DESIRED_PERF(ratio_2_msr_perf(hwp_req->hwp_desired)); - msr |= HWP_ENERGY_PERF_PREFERENCE(hwp_req->hwp_epp); - msr |= HWP_ACTIVITY_WINDOW(hwp_req->hwp_window); - msr |= HWP_PACKAGE_CONTROL(hwp_req->hwp_use_pkg); - - put_msr(cpu, msr_offset, msr); + if (genuine_intel) { + msr |= HWP_MIN_PERF(ratio_2_msr_perf(hwp_req->hwp_min)); + msr |= HWP_MAX_PERF(ratio_2_msr_perf(hwp_req->hwp_max)); + msr |= HWP_DESIRED_PERF(ratio_2_msr_perf(hwp_req->hwp_desired)); + msr |= HWP_ENERGY_PERF_PREFERENCE(hwp_req->hwp_epp); + msr |= HWP_ACTIVITY_WINDOW(hwp_req->hwp_window); + msr |= HWP_PACKAGE_CONTROL(hwp_req->hwp_use_pkg); + put_msr(cpu, msr_offset, msr); + } else if (authentic_amd) { + /* AMD EPP need to set desired perf with zero */ + hwp_req->hwp_desired = 0; + msr |= AMD_CPPC_MIN_PERF(hwp_req->hwp_min); + msr |= AMD_CPPC_MAX_PERF(hwp_req->hwp_max); + msr |= AMD_CPPC_DES_PERF(hwp_req->hwp_desired); + msr |= AMD_CPPC_ENERGY_PERF_PREF(hwp_req->hwp_epp); + amd_put_msr(cpu, msr_offset, (unsigned int)msr); + } } static int get_epb(int cpu) @@ -1157,8 +1166,12 @@ int update_hwp_request(int cpu) { struct msr_hwp_request req; struct msr_hwp_cap cap; + int msr_offset = 0; - int msr_offset = MSR_HWP_REQUEST; + if (genuine_intel) + msr_offset = MSR_HWP_REQUEST; + else if (authentic_amd) + msr_offset = MSR_AMD_CPPC_REQ; read_hwp_request(cpu, &req, msr_offset); if (debug) @@ -1181,7 +1194,11 @@ int update_hwp_request(int cpu) req.hwp_use_pkg = req_update.hwp_use_pkg; - read_hwp_cap(cpu, &cap, MSR_HWP_CAPABILITIES); + if (genuine_intel) + read_hwp_cap(cpu, &cap, MSR_HWP_CAPABILITIES); + else if (authentic_amd) + read_hwp_cap(cpu, &cap, MSR_AMD_CPPC_CAP1); + if (debug) print_hwp_cap(cpu, &cap, ""); @@ -1203,8 +1220,12 @@ int update_hwp_request_pkg(int pkg) struct msr_hwp_request req; struct msr_hwp_cap cap; int cpu = first_cpu_in_pkg[pkg]; + int msr_offset = 0; - int msr_offset = MSR_HWP_REQUEST_PKG; + if (genuine_intel) + msr_offset = MSR_HWP_REQUEST_PKG; + else if (authentic_amd) + msr_offset = MSR_AMD_CPPC_REQ; read_hwp_request(cpu, &req, msr_offset); if (debug) @@ -1225,7 +1246,11 @@ int update_hwp_request_pkg(int pkg) if (update_hwp_epp) req.hwp_epp = req_update.hwp_epp; - read_hwp_cap(cpu, &cap, MSR_HWP_CAPABILITIES); + if (genuine_intel) + read_hwp_cap(cpu, &cap, MSR_HWP_CAPABILITIES); + else if (authentic_amd) + read_hwp_cap(cpu, &cap, MSR_AMD_CPPC_CAP1); + if (debug) print_hwp_cap(cpu, &cap, ""); @@ -1246,13 +1271,27 @@ int update_hwp_request_pkg(int pkg) int enable_hwp_on_cpu(int cpu) { unsigned long long msr; + int ret; + + if (genuine_intel) { + get_msr(cpu, MSR_PM_ENABLE, &msr); + put_msr(cpu, MSR_PM_ENABLE, 1); + } else if (authentic_amd) { + ret = amd_get_msr(cpu, MSR_AMD_CPPC_ENABLE, (unsigned long *)(&msr)); + if (ret < 0) + errx(-1, "failed to get msr with return %d", ret); - get_msr(cpu, MSR_PM_ENABLE, &msr); - put_msr(cpu, MSR_PM_ENABLE, 1); + ret = amd_put_msr(cpu, MSR_AMD_CPPC_ENABLE, 1); + if (ret < 0) + errx(-1, "failed to put msr with return %d", ret); + } - if (verbose) + if (verbose && genuine_intel) printf("cpu%d: MSR_PM_ENABLE old: %d new: %d\n", cpu, (unsigned int) msr, 1); + if (verbose && authentic_amd) + printf("cpu%d: MSR_AMD_CPPC_ENABLE old: %d new: %d\n", cpu, (unsigned int) msr, 1); + return 0; }