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[209.132.180.67]) by mx.google.com with ESMTP id o22-v6si2743180pgk.534.2018.07.17.23.44.01; Tue, 17 Jul 2018 23:44:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CwceE8w+; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729058AbeGRHUS (ORCPT + 10 others); Wed, 18 Jul 2018 03:20:18 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:37757 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726830AbeGRHUS (ORCPT ); Wed, 18 Jul 2018 03:20:18 -0400 Received: by mail-wr1-f65.google.com with SMTP id q10-v6so3438823wrd.4 for ; Tue, 17 Jul 2018 23:43:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=RbEbuj6f++mKBQ5MixrgklOP10QoklsnpQVeI2hzmS0=; b=CwceE8w+AoI2wNauLMctOz0WBAYSod543iAzXxWROaxWJVOuwYbwpuSQo0oaUvDRLf 8Ns14bVMbuDRsmFyuR1Vv12XknYsjI6n1IQ71oOMZAt3oBCrnKVquM1iqbz+hvEDd5rI xL0hvjAD/Iib6LP7662pfnvQPcmyC/Ydg+wMU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=RbEbuj6f++mKBQ5MixrgklOP10QoklsnpQVeI2hzmS0=; b=i8DXFeWJDWnkTtvGCuEE/Z0BYGF3Mz5X2EEYan0qHq4CWonULxpV7LHVyX4ngi4a6s RC0a0FjYGFCVlPRp35j/9qRFfV3zgGpsZN8ssDB77F0GdyF2/65tyqpWVvWQ7dIC9mnT x0ELYzJ396mntBjvYasRkPLDYp3N8dBdjWQXLfIeJoSpTOIpDovcFnFwz8f4m5T/AizZ hWQs7qyF/G09jwwm7uEQiE+bJjeK07zSqlwTqlPHrggfpgg6l3z+YYj3CVLBnLIO9x1+ FNUDuCLKjMvbAgXbyo2H2lMXk2s8u6eYPkRzKwvz5vIa+1Mo8YQTxNSmypnBsafZE5XN CrhQ== X-Gm-Message-State: AOUpUlH4ZbxX7Pxy7v9o8Tx9gHAU6QJmEfol+ZTWwQx9i3PA8JrhspKL MUka6ezMltz800QukrRDtIsVIbGR3AM= X-Received: by 2002:adf:c08c:: with SMTP id d12-v6mr3246466wrf.268.1531896239238; Tue, 17 Jul 2018 23:43:59 -0700 (PDT) Received: from localhost ([103.249.91.115]) by smtp.gmail.com with ESMTPSA id z7-v6sm1891350wrh.85.2018.07.17.23.43.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 17 Jul 2018 23:43:58 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, vivek.gautam@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, Zhang Rui , linux-pm@vger.kernel.org Subject: [PATCH v8 3/7] thermal: tsens: Add support to split up register address space into two Date: Wed, 18 Jul 2018 12:13:09 +0530 Message-Id: <767b27da206b19fe3c957c105a2326f736e14367.1531895128.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org There are two banks of registers for v2 TSENS IPs: SROT and TM. On older SoCs these were contiguous, leading to DTs mapping them as one register address space of size 0x2000. In newer SoCs, these two banks are not contiguous anymore. Add logic to init_common() to differentiate between old and new DTs and adjust associated offsets for the TM register bank so that the old DTs will continue to function correctly. Signed-off-by: Amit Kucheria Reviewed-by: Bjorn Andersson Tested-by: Matthias Kaehlcke Reviewed-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson --- drivers/thermal/qcom/tsens-8996.c | 4 ++-- drivers/thermal/qcom/tsens-common.c | 12 ++++++++++++ drivers/thermal/qcom/tsens.h | 1 + 3 files changed, 15 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/thermal/qcom/tsens-8996.c b/drivers/thermal/qcom/tsens-8996.c index e1f7781..3e60cec 100644 --- a/drivers/thermal/qcom/tsens-8996.c +++ b/drivers/thermal/qcom/tsens-8996.c @@ -16,7 +16,7 @@ #include #include "tsens.h" -#define STATUS_OFFSET 0x10a0 +#define STATUS_OFFSET 0xa0 #define LAST_TEMP_MASK 0xfff #define STATUS_VALID_BIT BIT(21) #define CODE_SIGN_BIT BIT(11) @@ -28,7 +28,7 @@ static int get_temp_8996(struct tsens_device *tmdev, int id, int *temp) unsigned int sensor_addr; int last_temp = 0, last_temp2 = 0, last_temp3 = 0, ret; - sensor_addr = STATUS_OFFSET + s->hw_id * 4; + sensor_addr = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * 4; ret = regmap_read(tmdev->map, sensor_addr, &code); if (ret) return ret; diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index b1449ad..c22dc18 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include "tsens.h" @@ -126,11 +127,22 @@ static const struct regmap_config tsens_config = { int __init init_common(struct tsens_device *tmdev) { void __iomem *base; + struct platform_device *op = of_find_device_by_node(tmdev->dev->of_node); + if (!op) + return -EINVAL; base = of_iomap(tmdev->dev->of_node, 0); if (!base) return -EINVAL; + /* The driver only uses the TM register address space for now */ + if (op->num_resources > 1) { + tmdev->tm_offset = 0; + } else { + /* old DTs where SROT and TM were in a contiguous 2K block */ + tmdev->tm_offset = 0x1000; + } + tmdev->map = devm_regmap_init_mmio(tmdev->dev, base, &tsens_config); if (IS_ERR(tmdev->map)) { iounmap(base); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index dc56e1e..d785b37 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -77,6 +77,7 @@ struct tsens_device { struct device *dev; u32 num_sensors; struct regmap *map; + u32 tm_offset; struct tsens_context ctx; const struct tsens_ops *ops; struct tsens_sensor sensor[0];